IP Library Granted Patent US 10,475,995
Granted Patent B2
US 10,475,995 · App. 15/853,697 · Granted Nov 12, 2019

Tip-contact controlled three dimensional (3D) vertical self select memory

Inventor: Paolo Fantini (Vimercate, IT)
Assignee: Intel Corporation
H01L45/1233G11C13/003G11C13/0004H01L27/249H01L45/04H01L45/06H01L45/1226H01L45/1273H01L45/16H01L45/1616H01L45/1625B82Y35/00B82Y40/00G11C13/0026G11C2213/71G11C2213/72G11C2213/76H01L27/2427H01L45/144H01L45/146H01L45/149
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Quick Facts
Patent No.
US 10,475,995
App. No.
15/853,697
Granted
Nov 12, 2019
Kind
B2
Abstract

A variable resistance memory cell with a wide difference (“window”) between threshold voltages is provided. The window between threshold voltages is increased by amplifying the stoichiometry gradient by means of an asymmetry in the memory cell architecture to provide a greater margin for detecting different logic states of the memory cell.

Claims (18)

1. A memory comprising:

a first conductive layer comprising a first conductive material;

a second conductive layer comprising a second conductive material on top of the first conductive layer;

a third conductive layer comprising the first conductive material on top of the second conductive layer; and

an insulating layer formed in a first recess in the first conductive layer and a second recess in the third conductive layer to provide a tip contact with a selector material and the second conductive layer, the selector material formed in a third recess in the second conductive layer, a funnel shaped recess in the first conductive layer, a portion of the third conductive layer and a portion of the insulating layer.

2. The memory of claim 1 , wherein the selector material is aligned with a dielectric layer adjacent to a sidewall of a pillar opening and the first and second conductive layers.

3. The memory of claim 2 , wherein the insulating layer comprises aluminum oxide.

4. The memory of claim 3 , wherein the insulating layer is about 10 nanometers (nm) thick.

5. A system comprising:

a processor; and

a memory communicatively coupled to the memory, the memory comprising:

a first conductive layer comprising a first conductive material;

a second conductive layer comprising a second conductive material on top of the second conductive layer;

a third conductive layer comprising the first conductive material on top of the first conductive layer; and

an insulating layer formed in a first recess in the first conductive layer and a second recess in the third conductive layer to provide a tip contact with a selector material and the second conductive layer, the selector material formed in a third recess in the second conductive layer, a funnel shaped recess in the first conductive layer, a portion of the third conductive layer and a portion of the insulating layer.

6. The system of claim 5 , wherein the selector material is aligned with a dielectric layer adjacent to a sidewall of a pillar opening and the first and second conductive layers.

7. The system of claim 6 , wherein the dielectric layer comprises aluminum oxide.

8. The system of claim 6 , wherein the dielectric layer is about 10 nanometers (nm) thick.

Continuity (1)
Related Publication 20190044062A1 · Feb 7, 2019
Cited By (2)
US 12,419,059 US 12,432,934