Method of forming staircase structures for three-dimensional memory device double-sided routing

1. A method for forming a three-dimensional (3D) memory device, comprising:

forming a first dielectric layer on a substrate and a first photoresist layer on the first dielectric layer;

patterning a recess through the first dielectric layer to the substrate by a plurality cycles of trimming the first photoresist layer and etching the first dielectric layer;

forming a plurality of dielectric/sacrificial layer pairs filling in the recess;

forming a second photoresist layer on a top surface of the plurality of dielectric/sacrificial layer pairs;

patterning the plurality of dielectric/sacrificial layer pairs by a plurality cycles of trimming the second photoresist layer and etching the plurality of dielectric/sacrificial layer pairs;

forming a second dielectric layer covering the patterned plurality of dielectric/sacrificial layer pairs; and

forming a memory stack on the substrate comprising a plurality of conductor/dielectric layer pairs by replacing, with a plurality of conductor layers, the sacrificial layers in the patterned dielectric/sacrificial layer pairs.

2. The method of claim 1 , wherein forming the first dielectric layer comprises depositing a silicon oxide film.

3. The method of claim 1 , wherein patterning the recess comprises:

patterning the first photoresist layer to expose a portion of the first dielectric layer;

etching the exposed portion of the first dielectric layer using the patterned first photoresist layer as an etch mask;

trimming the first photoresist layer to enlarge the exposed portion of the first dielectric layer;

etching the enlarged exposed portion of the first dielectric layer using the trimmed first photoresist layer as another etch mask to form a step structure at an edge of the recess; and

repeating the cycle of trimming and etching until the etching reaches the substrate and resulting in a plurality of step structures at the edge of the recess.

4. The method of claim 3 , wherein in each cycle of trimming and etching, an amount of the trimmed first photoresist layer is the same.

5. The method of claim 3 , wherein forming the plurality of dielectric/sacrificial layer pairs comprises:

alternatingly depositing dielectric layers and sacrificial layers, wherein a thickness of each of the dielectric/sacrificial layer pairs is the same as a thickness of each of the step structures at the edge of the recess; and

planarizing the deposited dielectric layers and sacrificial layers until the top surface the dielectric/sacrificial layer pairs is flush with a top surface of the first dielectric layer.

6. The method of claim 1 , wherein patterning the plurality of dielectric/sacrificial layer pairs comprises:

patterning the second photoresist layer to expose a portion of a first one of the dielectric/sacrificial layer pairs;

etching the exposed portion of the first dielectric/sacrificial layer pair using the patterned second photoresist layer as an etch mask to expose a portion of a second one of the dielectric/sacrificial layer pairs;

trimming the second photoresist layer to expose another portion of the first dielectric/sacrificial layer pair;

etching the exposed portions of the first and second dielectric/sacrificial layer pairs using the trimmed second photoresist layer as another etch mask to form a step structure at an edge of the dielectric/sacrificial layer pairs; and

repeating the cycle of trimming and etching until the etching reaches the substrate and results in a plurality of step structures at the edge of the dielectric/sacrificial layer pairs.

7. The method of claim 6 , wherein in each cycle of trimming and etching, an amount of the trimmed second photoresist layer is the same.

8. The method of claim 1 , wherein forming the second dielectric layer comprises:

depositing a silicon oxide film; and

planarizing the silicon oxide film.

9. The method of claim 1 , wherein forming the memory stack comprises:

etching a plurality of openings through the patterned plurality of dielectric/sacrificial layer pairs;

etching the sacrificial layers in the patterned plurality of dielectric/sacrificial layer pairs through the plurality of openings; and

depositing the conductor layers in the plurality of conductor/dielectric layer pairs through the plurality of openings.

10. A method for forming staircase structures of a three-dimensional (3D) memory device, comprising:

forming a dielectric layer on a substrate and a photoresist layer on the dielectric layer;

patterning a recess through the dielectric layer to the substrate by a plurality cycles of trimming the photoresist layer and etching the dielectric layer, such that a top aperture of the patterned recess is larger than a bottom aperture of the patterned recess, and a plurality of step structures are formed at one edge of the patterned recess; and

forming a plurality of dielectric/sacrificial layer pairs filling in the patterned recess, such that a staircase structure is formed at one edge of the plurality of dielectric/sacrificial layer pairs.

11. The method of claim 10 , wherein the aperture of the patterned recess incrementally decreases from top to bottom.

12. The method of claim 10 , wherein patterning the recess comprises:

patterning the photoresist layer to expose a portion of the dielectric layer;

etching the exposed portion of the dielectric layer using the patterned photoresist layer as an etch mask;

trimming the photoresist layer to enlarge the exposed portion of the dielectric layer;

etching the enlarged exposed portion of the dielectric layer using the trimmed photoresist layer as another etch mask; and

repeating the cycle of trimming and etching until the etching reaches the substrate.

13. The method of claim 10 , wherein a depth of each of the plurality of step structures is the same.

14. The method of claim 13 , wherein forming the plurality of dielectric/sacrificial layer pairs comprises alternatingly depositing dielectric layers and sacrificial layers, wherein a thickness of each of the dielectric/sacrificial layer pairs is the same as the depth of each of the first and second plurality of step structures.

15. The method of claim 14 , wherein forming the plurality of dielectric/sacrificial layer pairs comprises planarizing the deposited dielectric layers and sacrificial layers until a top surface of the dielectric/sacrificial layer pairs flushes with a top surface of the dielectric layer.

16. A method for forming staircase structures of a three-dimensional (3D) memory device, comprising:

forming a dielectric layer on a substrate and a photoresist layer on the dielectric layer;

patterning a recess through the dielectric layer to the substrate by a plurality cycles of trimming the first photoresist layer and etching the dielectric layer;

forming a plurality of dielectric/sacrificial layer pairs filling in the recess, such that a top surface of the plurality of dielectric/sacrificial layer pairs flushes with a top surface of the dielectric layer, and a first staircase structure is formed at a first edge of the plurality of dielectric/sacrificial layer pairs;

forming a second photoresist layer on the top surface of the dielectric/sacrificial layer pairs; and

patterning the plurality of dielectric/sacrificial layer pairs by a plurality cycles of trimming the second photoresist layer and etching the plurality of dielectric/sacrificial layer pairs, such that a second staircase structure is formed at a second edge opposite to the first edge of the plurality of dielectric/sacrificial layer pairs.

17. The method of claim 16 , wherein patterning the recess comprises:

patterning the first photoresist layer to expose a portion of the dielectric layer;

etching the exposed portion of the dielectric layer using the patterned first photoresist layer as an etch mask;

trimming the first photoresist layer to enlarge the exposed portion of the dielectric layer;

etching the enlarged exposed portion of the dielectric layer using the trimmed first photoresist layer as another etch mask to form a step structure at one edge of the recess, respectively; and

repeating the cycle of trimming and etching until the etching reaches the substrate and resulting in a plurality of step structures at the one edge of the recess.

18. The method of claim 17 , wherein in each cycle of trimming and etching, an amount of the trimmed first photoresist layer is the same.

19. The method of claim 17 , wherein a depth of each of the plurality of step structures is the same.

20. The method of claim 16 , wherein patterning the plurality of dielectric/sacrificial layer pairs comprises:

patterning the second photoresist layer to expose a portion of a first one of the dielectric/sacrificial layer pairs;

etching the exposed portion of the first dielectric/sacrificial layer pair using the patterned second photoresist layer as an etch mask to expose a portion of a second one of the dielectric/sacrificial layer pairs;

trimming the second photoresist layer to expose another portion of the first dielectric/sacrificial layer pair;

etching the exposed portions of the first and second dielectric/sacrificial layer pairs using the trimmed second photoresist layer as another etch mask; and

repeating the cycle of trimming and etching until the etching reaches the substrate.