IP Library Granted Patent US 10,483,391
Granted Patent B2
US 10,483,391 · App. 15/845,628 · Granted Nov 19, 2019

Semiconductor device and method for manufacturing the same

Inventor: Takahiro Mori (Hitachinaka, JP)
Assignee: RENESAS ELECTRONICS CORPORATION
H01L29/7825H01L29/0653H01L29/0692H01L29/1095H01L29/402H01L29/408H01L29/4236H01L29/66659H01L29/66704H01L29/7835H01L29/1045
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Quick Facts
Patent No.
US 10,483,391
App. No.
15/845,628
Granted
Nov 19, 2019
Kind
B2
Abstract

A semiconductor device according to one embodiment includes a semiconductor substrate having a first surface, an insulating isolation film disposed at the first surface, and a gate electrode. The semiconductor substrate has a source region, a drain region, a drift region, and a body region. The insulating isolation film has a first portion disposed inside the drift region in plan view, a second portion protruding from the first portion in a direction toward the source region, and a third portion protruding from the first portion in the direction toward the source region and sandwiching the drift region between the second portion and the third portion. The gate electrode faces a portion of the body region sandwiched between the source region and the drift region with being insulated from the portion. The gate electrode is disposed so as to extend over the second portion and the third portion.

Claims (27)

1. A semiconductor device comprising:

a semiconductor substrate having a first surface;

an insulating isolation film disposed at the first surface; and

a gate electrode,

the semiconductor substrate having a source region disposed in contact with the first surface, a drain region disposed in contact with the first surface, a drift region disposed in contact with the first surface so as to surround the drain region, and a body region sandwiched between the drift region and the source region and disposed in contact with the first surface so as to surround the source region,

the source region, the drain region, and the drift region being of a first conductivity type,

the body region being of a second conductivity type which is opposite to the first conductivity type,

the insulating isolation film having a first portion disposed inside the drift region in plan view, a second portion protruding from the first portion in a direction toward the source region, and a third portion protruding from the first portion in the direction toward the source region and sandwiching the drift region between the second portion and the third portion,

the gate electrode facing a portion of the body region sandwiched between the source region and the drift region with being insulated from the portion, and being disposed so as to extend over the second portion and the third portion, wherein

the semiconductor substrate has a second surface opposite to the first surface,

the gate electrode has a first embedded portion embedded in the second portion, and a second embedded portion embedded in the third portion,

the drift region is sandwiched between the first embedded portion and the second embedded portion, and

the gate electrode has a third embedded portion embedded in the first portion and facing the drift region sandwiched between the second portion and the third portion.

2. The semiconductor device according to claim 1 , wherein each of an end of the first embedded portion and an end of the second embedded portion closer to the drain region is located closer to the drift region, than a midpoint between an end of the first portion closer to the drain region and an end of the first portion closer to the drift region.

3. The semiconductor device according to claim 1 , wherein the second portion located between the first embedded portion and the drift region sandwiched between the second portion and the third portion has a width of less than or equal to 0.3 μm.

4. The semiconductor device according to claim 1 , wherein the first embedded portion has a depth which is more than or equal to 0.25 times a depth of the insulating isolation film.

5. The semiconductor device according to claim 1 , wherein

the first embedded portion is embedded in a first trench extending toward the second surface in the second portion,

the second embedded portion is embedded in a second trench extending toward the second surface in the third portion,

the third embedded portion is embedded in a third trench extending toward the second surface in the first portion, and

the first trench, the second trench, and the third trench are separated from one another.

6. The semiconductor device according to claim 1 , wherein

the third embedded portion extends toward a channel width direction which is a direction intersecting with a direction from the source region toward the drain region, and

an end of the third embedded portion in the channel width direction is located more outward than an end of the drain region in the channel width direction.

7. The semiconductor device according to claim 1 , wherein

the second portion is disposed more outward than an end of the drain region in a channel width direction which is a direction intersecting with a direction from the source region toward the drain region, and

the third portion is disposed more inward than the end of the drain region in the channel width direction.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 19, 2017
From: MORI, TAKAHIRO
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044432/0442 →
Priority Claims (1)
JP 2016-255178 · Dec 28, 2016 · national
Continuity (1)
Related Publication 20180182890A1 · Jun 28, 2018