Multi-bit successive-approximation register analog-to-digital converter

1. A system for digitizing a sampled input value, comprising:

a digital-to-analog converter for generating an output signal as a function of (1) the sampled input value, (2) a reference value, and (3) digital codes; and

a multi-bit analog-to-digital converter for determining the digital codes in first, intermediate, and subsequent cycles;

wherein dither is dynamically added to the digital-to-analog converter in the intermediate cycle, and corrected for in the subsequent cycle.

2. The system of claim 1 , wherein the digital-to-analog converter includes capacitors for adjusting the output signal under the control of the digital codes.

3. The system of claim 2 , further comprising an amplifier for amplifying the output signal and for applying an amplified signal to the analog-to-digital converter.

4. The system of claim 3 , wherein the analog-to-digital converter includes a logic and timing circuit for controlling the amplifier and for applying the digital codes to the capacitors of the digital-to-analog converter.

5. The system of claim 4 , wherein the logic and timing circuit causes a dither voltage to be applied to one of the capacitors during the intermediate cycle, and wherein the dither voltage is not applied to the capacitors before or after the intermediate cycle.

6. A system for digitizing an analog input voltage, comprising:

a digital-to-analog converter for generating an output voltage as a function of (1) the input voltage, (2) a reference voltage, and (3) digital codes, wherein the digital-to-analog converter includes a capacitor array which is responsive to the digital codes; and

a multi-bit successive-approximation register analog-to-digital converter for receiving the output voltage and determining the digital codes based on the output voltage in first, intermediate, and subsequent cycles;

wherein the capacitor array has a dither capacitor to which dither is dynamically added during the intermediate cycle; and

wherein dither is not applied to the dither capacitor during the subsequent cycle, and wherein the digital codes are corrected for by the analog-to-digital converter during the subsequent cycle.

7. The system of claim 6 , further comprising an input line for supplying the input voltage to the digital-to-analog converter.

8. The system of claim 7 , wherein the capacitor array further includes most-significant-bit capacitors, least-significant-bit capacitors, and an additional capacitor, and wherein least-significant-bit codes for the least-significant-bit capacitors are determined during the intermediate cycle while dither is applied to the dither capacitor, and wherein a digital code for correcting the least-significant-bit codes is determined during the subsequent cycle while dither is not applied to the dither capacitor.

9. The system of claim 8 , further comprising an amplifier for amplifying the output voltage and applying an amplified voltage to the analog-to-digital converter.

10. The system of claim 9 , wherein the analog-to-digital converter includes a flash device for receiving the amplified voltage.

11. The system of claim 9 , further comprising a steering current source for applying a digital code to the capacitor array.

12. The system of claim 9 , wherein the analog-to-digital converter includes a logic and timing circuit for controlling gain of the amplifier.

13. A method of digitizing an analog input voltage, comprising:

sampling the input voltage;

subsequently, in a first cycle, using a capacitor array to generate a first output voltage as a function of (1) the input voltage, (2) a reference voltage, and (3) digital codes, and using a multi-bit successive-approximation register analog-to-digital converter to determine first digital codes;

subsequently, in an intermediate cycle, dynamically adding dither to a capacitor of the capacitor array to reduce the formation of higher-order harmonics in an output signal, using the capacitor array to generate an intermediate output voltage as a function of the input voltage, a reference voltage, and the first digital codes, and using the multi-bit successive-approximation register analog-to-digital converter to determine second digital codes;

subsequently, using the capacitor array to generate a subsequent output voltage as a function of the input voltage, a reference voltage, and the first and second digital codes, and using the multi-bit successive-approximation register analog-to-digital converter to determine a third digital code for correcting the second digital codes; and

subsequently, using the first, second, and third digital codes to cause the output signal to be representative of the input voltage.

14. The method of claim 13 , further comprising sampling a new input voltage and applying the new input voltage to the capacitor array.

15. The method of claim 13 , wherein the capacitor array includes most-significant-bit capacitors, least-significant-bit capacitors, and an additional capacitor, and wherein least-significant-bit codes for the least-significant-bit capacitors are determined during the intermediate cycle while dither is applied to the capacitor array, and wherein a digital code for correcting the least-significant-bit codes is determined during the subsequent cycle while dither is not applied to the capacitor array.

16. The method of claim 13 , further comprising amplifying the output voltages and applying amplified voltages to the analog-to-digital converter.

17. The system of claim 16 , further comprising using a logic and timing circuit for controlling gain of the amplifier.

18. The method of claim 17 , wherein the analog-to-digital converter includes a flash device for receiving the amplified voltage.

19. The method of claim 13 , further comprising using a steering current source for applying the third digital code to the capacitor array.

20. The method of claim 13 , wherein the causing of the output signal to be representative of the input voltage includes decoding the first, second, and third digital codes.