Hypervisor direct memory access
This disclosure generally relates to hypervisor memory virtualization. Techniques disclosed herein improve peripheral component interconnect express (PCI-e) device interoperability with a virtual machine. As an example, when a direct-memory access request is received from a PCI-e device but the target memory is currently unmapped, an indication may be provided to a memory paging processor so as to page-in the memory, such that the PCI-e device may continue to function normally. In some examples, the access request may be buffered and replayed once the memory is paged-in, or the access request may be retried, among other examples.
1. A system comprising:
at least one processor; and
a first memory storing instructions that, when executed by the at least one processor, perform a method for providing direct memory access, comprising:
identifying a direct memory access request for one or more pages of a second memory by a peripheral device;
communicating with a memory paging processor to determine whether the requested one or more pages are unmapped in the second memory;
based on determining that the requested one or more pages are unmapped in the second memory:
storing at least a part of the direct memory access request in a third memory as a buffered the direct memory access request; and
generating a request to the memory paging processor to page-in the one or more pages;
receiving, from the memory paging processor, an indication that the one or more pages are available in the second memory; and
in response to the indication that the one or more pages are available in the second memory, using the buffered direct memory access request, without requiring a retry direct memory access request from the peripheral device, to resume direct memory access by the peripheral device.
2. The system of claim 1 , wherein the direct memory access request is identified based on an indication received from an input-output memory management unit.
3. The system of claim 1 , wherein, based on resuming the direct memory access request, a retry direct memory access request for the one or more pages of memory is not received from the peripheral device.
4. The system of claim 1 , wherein the second memory and the third memory are subparts of a fourth memory.
5. The system of claim 1 , wherein the peripheral device is a peripheral component interconnect express device.
6. The system of claim 1 , wherein the request to the memory paging processor comprises at least one memory address associated with the one or more pages.
7. The system of claim 1 , wherein the direct memory access request is identified as a result of a virtual machine interacting with the peripheral device.
8. A method for providing direct memory access for a device in use by a virtual machine, comprising:
identifying, as a result of a transaction between the device and the virtual machine, a memory access request for one or more pages of a first memory by the device;
communicating with a memory paging processor to determine whether the requested one or more pages are unmapped in the first memory;
based on determining that the requested one or more pages are unmapped in the first memory:
buffering at least a part of the memory access request in a second memory as a buffered memory access request; and
generating a request to the memory paging processor to page-in the one or more pages;
receiving, from the memory paging processor, an indication that the one or more pages are available in the first memory;
in response to the indication that the one or more pages are available in the first memory, continuing the transaction based on the buffered memory access request without requiring a retry memory access request from the device.
9. The method of claim 8 , wherein the memory access request is identified based on an indication received from an input-output memory management unit.
10. The method of claim 8 , wherein, based on continuing the transaction, a retry memory access request for the one or more pages of memory is not received from the device.
11. The method of claim 8 , wherein the first memory and the second memory are subparts of a third memory.
12. The method of claim 8 , wherein the request to the memory paging processor comprises at least one memory address associated with the one or more pages.
13. The method of claim 8 , wherein the device is a peripheral component interconnect express device.
14. A method for providing direct memory access, comprising:
identifying a memory access request for one or more pages of a first memory by a peripheral device;
communicating with a memory paging processor to determine whether the requested one or more pages are unmapped in the first memory;
based on determining that the requested one or more pages are unmapped in the first memory:
storing at least a part of the memory access request in a second memory as a buffered memory access request; and
generating a request to the memory paging processor to page-in the one or more pages;
receiving, from the memory paging processor, an indication that the one or more pages are available in the first memory; and
in response to the indication that the one or more pages are available in the first memory, using the buffered memory access request, without requiring a retry memory access request from the peripheral device, to resume the memory access request for the one or more pages of the first memory.
15. The method of claim 14 , wherein the memory access request is identified based on an indication received from an input-output memory management unit.
16. The method of claim 14 , wherein the first memory and the second memory are subparts of a third memory.
17. The method of claim 14 , wherein the peripheral device is a peripheral component interconnect express device.
18. The method of claim 15 , wherein the request to the memory paging processor comprises at least one memory address associated with the one or more pages.
19. The method of claim 18 , wherein the at least one memory address is a physical memory address or a virtual memory address.
20. The method of claim 14 , wherein the memory access request is identified as a result of a virtual machine interacting with the peripheral device.