Apparatus for sampling electrical signals with improved hold time and associated methods
An apparatus includes a sample-and-hold (S/H) circuit. The S/H circuit includes a first switch to provide an input signal that is to be sampled, and a second switch coupled to receive the sampled signal. The second switch is further coupled to a capacitor. The S/H circuit further includes at least one native transistor coupled to the second switch and to the capacitor.
1. An apparatus, comprising:
a sample-and-hold (S/H) circuit, comprising:
a first switch to provide an input signal that is to be sampled;
a second switch coupled to receive the input signal, the second switch further coupled to a capacitor;
a third switch coupled to a ground of the S/H circuit and to a node between the first and second switches; and
a first native transistor coupled to the second switch and to the capacitor.
2. The apparatus according to claim 1 , wherein the third switch is closed during a hold mode of the S/H circuit.
3. The apparatus according to claim 1 , wherein the third switch is open during a sample mode of the S/H circuit.
4. The apparatus according to claim 1 , wherein the first switch comprises a first metal semiconductor field effect transistor (MOSFET), and wherein the second switch comprises a second MOSFET.
5. The apparatus according to claim 4 , wherein during a hold mode of the S/H circuit, a gate of the first native transistor is coupled to a drain of the second MOSFET, and wherein a source of the first native transistor is coupled to a bulk of the second MOSFET.
6. The apparatus according to claim 5 , further comprising a second native transistor having a source coupled to a gate of the second MOSFET and a gate coupled to the drain of the second MOSFET.
7. The apparatus according to claim 5 , wherein a source of the first MOSFET is coupled to receive the input signal, and wherein a drain of the first MOSFET is coupled to a source of the second MOSFET.
8. The apparatus according to claim 1 , further comprising an input circuit to accept the input signal and to couple the input signal to the first switch.
9. An apparatus, comprising:
a sample-and-hold (S/H) circuit, comprising:
a first switch to provide an input signal that is to be sampled;
a second switch coupled to receive the input signal, the second switch further coupled to an output node of the S/H circuit;
a first native transistor coupled to the second switch and to the output node of the S/H circuit; and
a second native transistor coupled to the second switch and to the output node of the S/H circuit.
10. The apparatus according to claim 9 , further comprising a capacitor coupled to the output node of the S/H circuit.
11. The apparatus according to claim 10 , wherein the first switch comprises a first metal oxide semiconductor field effect transistor (MOSFET), and wherein the second switch comprises a second MOSFET.
12. The apparatus according to claim 11 , wherein a source of the first native transistor is coupled to a bulk of the second MOSFET, a drain of the first native transistor is coupled to a supply voltage, and a gate of the first native transistor is coupled to a drain of the second MOSFET.
13. The apparatus according to claim 11 , wherein a source of the second native transistor is coupled to a gate of the second MOSFET, a drain of the second native transistor is coupled to a supply voltage, and a gate of the second native transistor is coupled to a drain of the second MOSFET.
14. A method of using a sample and hold (S/H) circuit having a sample mode and a hold mode, the method comprising:
providing, by using a first switch, an input signal to be sampled;
using a second switch to provide the input signal to a capacitor;
grounding a node between the first and second switches by using a third switch during the hold mode of the S/H circuit; and
using a first native transistor coupled to the second switch to increase a hold time of the S/H circuit.
15. The method according to claim 14 , further comprising opening the third switch during the sample mode of the S/H circuit.
16. The method according to claim 14 , wherein using the first native transistor coupled to the second switch to increase the hold time of the S/H circuit further comprises reducing at least one leakage current in the S/H circuit.
17. The method according to claim 14 , further comprising using a second native transistor coupled to the second switch to increase the hold time of the S/H circuit.
18. The method according to claim 17 , wherein using the second native transistor coupled to the second switch to increase the hold time of the S/H circuit further comprises reducing a gate induced drain leakage current of the second transistor.
19. The method according to claim 14 , wherein grounding the node between the first and second switches by using the third switch during the hold mode of the S/H circuit comprises closing the third switch during the hold mode of the S/H circuit.
20. The method according to claim 14 , wherein providing, by using the first switch, the input signal to be sampled further comprises using an input circuit to accept the input signal and to couple the input signal to the first switch.