Optimized pin pattern for high speed input/output

1. An apparatus, comprising:

a pin pattern comprising a plurality of pins arranged in rows and columns in an interstitial pattern such that pins in each row are offset in a row direction relative the pins in adjacent rows, and pins in each column are offset in a column direction relative to the pins in adjacent columns,

wherein the plurality of pins comprise:

a plurality of isolation pins; and

a plurality of differential signal pairs, each differential signal pair comprising a first signal pin and a second signal pin, the first signal pin configured to carry a first differential signal, and the second signal pin configured to carry a second differential signal complementary to the first differential signal,

wherein the first signal pin and/or the second signal pin of each differential signal pair is an immediate neighbor pin of the first signal pin and/or the second signal pin of at least one other differential signal pair, and

wherein a net number of aggressor pins is zero for each of the first and second signal pins of each differential signal pair.

2. The apparatus of claim 1 ,

wherein each pin has a plurality of immediate neighbor pins,

wherein each pin is equidistant or substantially equidistant from each of its immediate neighbor pins, and

wherein a distance between any two immediate neighbor pins is equal to a distance between any other two immediate neighbor pins.

3. The apparatus of claim 1 , wherein the plurality of differential signal pairs are arranged such that the net number of aggressor pins is zero for each of the first and second signal pins of each differential signal pair through differential cancellation.

4. The apparatus of claim 3 ,

wherein a signal pin of at least one differential signal pair has as its immediate neighbor pins both the first and second signal pins of at least one other differential signal pair, the signal pin being one of the first signal pin and the second signal pin of the at least one differential signal pair,

wherein the signal pin of the at least one differential signal pair is equidistant or substantially equidistant to both the first and second signal pins of the at least one other differential signal pair such that first and second crosstalk effects cancel each other at the signal pin of the at least one differential signal pair, and

wherein the first crosstalk effect is a crosstalk effect due to a signal carried on the first signal pin of the at least one other differential signal pair, and the second crosstalk effect is a crosstalk effect due to a signal carried on the second signal pin of the at least one other differential signal pair.

5. The apparatus of claim 3 ,

wherein both the first and second signal pins of at least one differential signal pair have as one of their immediate neighbor pins a signal pin of at least one other differential signal pair, the signal pin being one of the first signal pin and the second signal pin of the at least one other differential signal pair,

wherein the first and second signal pins of the at least one differential signal pair are equidistant to the signal pin of the at least one other differential signal pair such that first and second crosstalk effects are canceled at the at least one differential signal pair, and

wherein the first crosstalk effect is a crosstalk effect due to a signal carried on the signal pin of the at least one other differential signal pair and experienced at the first signal pin of the at least one differential signal pair, and the second crosstalk effect is a crosstalk effect due to the signal carried on the signal pin of the at least one other differential signal pair and experienced at the second signal pin of the at least one differential signal pair.

6. The apparatus of claim 1 , wherein the pin pattern is repeated vertically, horizontally, or both.

7. The apparatus of claim 1 , wherein a signal-to-pin ratio is at least 0.4.

8. The apparatus of claim 1 ,

wherein the pin pattern is for a 2×16 HSIO (high speed input/output) segment, and

wherein a pin count for the 2×16 HSIO segment of the pin pattern is less than a pin count for 2×16 HSIO segment of a CCIX (Cache Coherent Interconnect for Accelerators) pin pattern.

9. The apparatus of claim 8 , wherein the pin count for the 2×16 HSIO segment of the pin pattern is 384 or less.

10. The apparatus of claim 1 , wherein the pin pattern is configured to operate at a speed of at least 25 Gbps (gigabits per second).

11. The apparatus of claim 1 , further comprising a plurality of routing paths configured to couple the plurality of differential signal pairs to outside of the apparatus,

wherein each routing path corresponds to one of the differential signal pairs, and

wherein the plurality of routing paths are provided in a layer of the apparatus.

12. The apparatus of claim 1 , wherein the apparatus is incorporated into a device selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, a networking device, a co-processing device, a storage device and a device in an automotive vehicle.

13. A method, comprising:

forming a pin pattern of an apparatus, the pin pattern comprising a plurality of pins, wherein forming the pin pattern comprises:

forming a plurality of isolation pins of the of pin pattern; and

forming a plurality of differential signal pairs of the pin pattern such that each differential signal pair comprises a first signal pin configured to carry a first differential signal and a second signal pin configured to carry a second differential signal complementary to the first differential signal,

wherein the pin pattern is formed such that the plurality of pins are arranged in rows and columns in an interstitial pattern such that pins in each row are offset in a row direction relative the pins in adjacent rows, and pins in each column are offset in a column direction relative to the pins in adjacent columns, and

wherein the plurality of differential signal pairs are arranged such that

the first signal pin and/or the second signal pin of each differential signal pair is an immediate neighbor pin of the first signal pin and/or the second signal pin of at least one other differential signal pair, and

a net number of aggressor pins is zero for each of the first and second signal pins of each differential signal pair.

14. The method claim 13 , wherein the pin pattern is formed such that

each pin has a plurality of immediate neighbor pins,

each pin is equidistant or substantially equidistant from each of its immediate neighbor pins, and

a distance between any two immediate neighbor pins is equal to a distance between any other two immediate neighbor pins.

15. The method claim 13 , wherein the plurality of differential signal pairs are arranged such that the net number of aggressor pins is zero for each of the first and second signal pins of each differential signal pair through differential cancellation.

16. The method of claim 15 , wherein the plurality of differential signal pairs are arranged such that

a signal pin of at least one differential signal pair has as its immediate neighbor pins both the first and second signal pins of at least one other differential signal pair, the signal pin being one of the first signal pin and the second signal pin of the at least one differential signal pair, and

the signal pin of the at least one differential signal pair is equidistant or substantially equidistant to both the first and second signal pins of the at least one other differential signal pair such that first and second crosstalk effects cancel each other at the signal pin of the at least one differential signal pair,

the first crosstalk effect being a crosstalk effect due to a signal carried on the first signal pin of the at least one other differential signal pair, and the second crosstalk effect being a crosstalk effect due to a signal carried on the second signal pin of the at least one other differential signal pair.

17. The method of claim 15 , wherein the plurality of differential signal pairs are arranged such that

both the first and second signal pins of at least one differential signal pair have as one of their immediate neighbor pins a signal pin of at least one other differential signal pair, the signal pin being one of the first signal pin and the second signal pin of the at least one other differential signal pair, and

the first and second signal pins of the at least one differential signal pair are equidistant or substantially equidistant to the signal pin of the at least one other differential signal pair such that first and second crosstalk effects are canceled at the at least one differential signal pair,

the first crosstalk effect being a crosstalk effect due to a signal carried on the signal pin of the at least one other differential signal pair and experienced at the first signal pin of the at least one differential signal pair, and the second crosstalk effect being a crosstalk effect due to the signal carried on the signal pin of the at least one other differential signal pair and experienced at the second signal pin of the at least one differential signal pair.

18. The method of claim 13 , wherein forming the pin pattern is repeated vertically, horizontally, or both.

19. The method of claim 13 ,

wherein the pin pattern is for a 2×16 HSIO (high speed input/output) segment, and

wherein the pin pattern is formed such that a pin count for the 2×16 HSIO segment of the pin pattern is less than a pin count for 2×16 HSIO segment of a COX (Cache Coherent Interconnect for Accelerators) pin pattern.

20. The method of claim 13 , further comprising forming a plurality of routing paths configured to couple the plurality of differential signal pairs to outside of the apparatus,

wherein each routing path corresponds to one of the differential signal pairs, and

wherein the plurality of routing paths are provided in a layer of the apparatus.