IP Library Granted Patent US 10,554,183
Granted Patent B2
US 10,554,183 · App. 16/244,913 · Granted Feb 4, 2020

Distortion compensation apparatus and distortion compensation method

Inventor: Yoshiaki Doi (Tokyo, JP)
Assignee: NEC CORPORATION
H03F1/3247H03F1/3258H03F1/3282H03F2201/3224H03F2201/3233
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Quick Facts
Patent No.
US 10,554,183
App. No.
16/244,913
Granted
Feb 4, 2020
Kind
B2
Abstract

A DPD operates at a sampling rate at which the input signal not up sampled at an upstream of the DPD is sampled. The DPD includes a polynomial structure comprising a pseudo-interpolation and sub-sample shift processing unit configured to pseudo-interpolate a sample point between the sample points of the input signal and shift the pseudo-interpolated sample point by a sub-sample, and an FIR (Finite Impulse Response) filter disposed at a downstream of the polynomial structure and including a sub-sample delay filter configured to delay the sample point of the input signal by the sub-sample. The DPD uses the polynomial structure and the FIR filter to compensate distortion by the sample point of the input signal and also compensate distortion by a sub-sample point between the sample points of the input signal for the digital predistorter.

Claims (42)

1. A distortion compensation apparatus for compensating non-linear distortion of a power amplifier, the distortion compensation apparatus comprising:

an AD converter configured to feed back an output signal of the power amplifier, convert it from analog to digital, and output the converted signal as a feedback signal;

a digital predistorter configured to perform distortion compensation processing on an input signal using the feedback signal and output a signal which has been subjected to the distortion compensation processing;

a DA converter disposed between the digital predistorter and the power amplifier and configured to convert the output signal of the digital predistorter from digital to analog and output the converted signal to the power amplifier, wherein

the digital predistorter operates at a sampling rate at which the input signal not upsampled at an upstream of the digital predistorter is sampled,

the digital predistorter comprises:

a polynomial structure comprising a pseudo-interpolation and sub-sample shift processing unit configured to pseudo-interpolate a sample point between the sample points of the input signal and shift the pseudo-interpolated sample point by a sub-sample; and

an FIR (Finite Impulse Response) filter disposed at a downstream of the polynomial structure and including a sub-sample delay filter configured to delay the sample point of the input signal by the sub-sample, and

the digital predistorter uses the polynomial structure and the FIR filter to compensate distortion by the sample point of the input signal and also compensate distortion by a sub-sample point between the sample points of the input signal for the digital predistorter.

2. The distortion compensation apparatus according to claim 1 , wherein

the digital predistorter comprises:

a plurality of the FIR filters; and

a first adder configured to add an output signal of each of the plurality of the FIR filters and output an added signal,

the digital predistorter includes a configuration in which a plurality of first paths of the polynomial structure are branched in parallel from an input stage of the digital predistorter, and the plurality of the FIR filters are disposed at a downstream of each of the plurality of first paths, and the first adder is disposed at a downstream of the plurality of FIR filters, and

the pseudo-interpolation and sub-sample shift processing unit is disposed in the first path.

3. The distortion compensation apparatus according to claim 2 , wherein the plurality of the first paths include the first path in which the pseudo-interpolation and sub-sample shift processing unit is disposed and the first path in which the pseudo-interpolation and sub-sample shift processing unit is not disposed.

4. The distortion compensation apparatus according to claim 3 , wherein

the pseudo-interpolation and sub-sample shift processing unit is a filter including a fixed tap coefficient, and

a first delay device including a delay amount determined by the number of taps of the pseudo-interpolation and sub-sample shift processing unit is disposed in the first path in which the pseudo-interpolation and sub-sample shift processing unit is not disposed.

5. The distortion compensation apparatus according to claim 2 , wherein

each of the plurality of the FIR filters includes a configuration in which a plurality of second paths are branched in parallel from the input stage of the FIR filter, and

the sub-sample delay filter is disposed in the second path.

6. The distortion compensation apparatus according to claim 5 , wherein the plurality of second paths include the second path in which the sub-sample delay filter is disposed and the second path in which the sub-sample delay filter is not disposed.

7. The distortion compensation apparatus according to claim 6 , wherein

the sub-sample delay filter is a filter including a fixed tap coefficient, and

a second delay device including a delay amount determined by the number of taps of the sub-sample delay filter is disposed in the second path in which the sub-sample delay filter is not disposed.

8. The distortion compensation apparatus according to claim 7 , wherein

each of the plurality of FIR filters comprises one-sample delay device configured to delay the sample point of the input signal by one sample,

in the second path in which the sub-sample delay filter is disposed, the one-sample delay device is disposed at a downstream of the sub-sample delay filter, and

in the second path in which the sub-sample delay filter is not disposed, the one-sample delay device is disposed at a downstream of the second delay device.

9. The distortion compensation apparatus according to claim 8 , wherein

each of the plurality of FIL filters comprises:

a plurality of multipliers configured to multiply each of output signals of the sub-sample delay filter, the second delay device, and the one-sample delay device by a corresponding filter coefficient; and

a second adder configured to add the output signal of each of the plurality of multipliers and output an added signal.

10. A distortion compensation method performed by a distortion compensation apparatus for compensating non-linear distortion of a power amplifier, the distortion compensation method comprising:

performing distortion compensation processing by a digital predistorter on an input signal using a feedback signal obtained by feeding back an output signal of the power amplifier and converting it from analog to digital and outputting the signal which has been subjected to the distortion compensation processing; and

converting the output signal of the digital predistorter from digital to analog and outputting the converted signal to the power amplifier, wherein

the digital predistorter operates at a sampling rate at which the input signal not upsampled at an upstream of the digital predistorter is sampled,

the digital predistorter comprises:

a polynomial structure comprising a pseudo-interpolation and sub-sample shift processing unit configured to pseudo-interpolate a sample point between the sample points of the input signal and shift the pseudo-interpolated sample point by a sub-sample; and

an FIR (Finite Impulse Response) filter disposed at a downstream of the polynomial structure and including a sub-sample delay filter configured to delay the sample point of the input signal by the sub-sample, and

the digital predistorter uses the polynomial structure and the FIR filter to compensate distortion by the sample point of the input signal and also compensate distortion by a sub-sample point between the sample points of the input signal for the digital predistorter.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 11, 2019
From: DOI, YOSHIAKI
To: NEC CORPORATION
Reel/Frame 047963/0599 →
Priority Claims (1)
JP 2018-003715 · Jan 12, 2018 · national
Continuity (1)
Related Publication 20190222179A1 · Jul 18, 2019