Trigger circuitry for fast, low-power state transitions
An n-type transistor and a p-type transistor are connected in series such that, when the two transistors are turned on, current flows from the collector of the n-type transistor to the collector of the p-type transistor. A positive-feedback capacitor is connected between the collector of one transistor and the base of the other transistor. The two transistors turn on together when the base voltage of the n-type transistor exceeds the base voltage of the p-type transistor by at least the sum of the turn-on threshold voltages of the two transistors and (i) the two transistors turn off together when the base voltage of the n-type transistor fails to exceed the base voltage of the p-type transistor by at least that sum. The positive-feedback capacitor ensures that the two transistors turn fully on and off together. In certain embodiments, the circuitry can be controlled to operate as a current pulse generator.
1. Circuitry comprising a trigger circuit, wherein the trigger circuit comprises:
an n-type transistor having a base, a collector, and an emitter and characterized by a turn-on threshold voltage;
a p-type transistor having a base, a collector, and an emitter and characterized by a turn-on threshold voltage, wherein the collector and emitter of the n-type transistor are connected in series with the collector and emitter of the p-type transistor such that, when the two transistors are turned on, current flows from the collector of the n-type transistor to the collector of the p-type transistor; and
a positive-feedback capacitor connected between the collector of a first of the two transistors and the base of a second of the two transistors, wherein:
the trigger circuit is configured such that (i) the two transistors turn on together when the voltage at the base of the n-type transistor exceeds the voltage at the base of the p-type transistor by at least the sum of the turn-on threshold voltages of the two transistors and (i) the two transistors turn off together when the voltage at the base of the n-type transistor fails to exceed the voltage at the base of the p-type transistor by at least the sum of the turn-on threshold voltages of the two transistors; and
the positive-feedback capacitor ensures that the two transistors turn fully on and off together.
2. The circuitry of claim 1 , wherein the two transistors are bipolar transistors or field-effect transistors.
3. The circuitry of claim 1 , wherein:
the first transistor is the n-type transistor;
the second transistor is the p-type transistor; and
the positive-feedback capacitor is connected between the collector of the n-type transistor and the base of the p-type transistor.
4. The circuitry of claim 3 , further comprising a timing capacitor connected to the base of the n-type transistor and configured to be charged when the two transistors are off and discharged when the two transistors are on, wherein:
the charging of the timing capacitor causes the two transistors to turn on; and
the discharging of the timing capacitor contributes to a current pulse through the two transistors.
5. The circuitry of claim 1 , wherein:
the first transistor is the p-type transistor;
the second transistor is the n-type transistor; and
the positive-feedback capacitor is connected between the collector of the p-type transistor and the base of the n-type transistor.
6. The circuitry of claim 5 , further comprising a timing capacitor connected to the base of the p-type transistor and configured to be charged when the two transistors are off and discharged when the two transistors are on, wherein:
the charging of the timing capacitor causes the two transistors to turn on; and
the discharging of the timing capacitor contributes to a current pulse through the two transistors.
7. The circuitry of claim 1 , wherein an output load is connected in series between the emitter of the n-type transistor and the emitter of the p-type transistor.
8. The circuitry of claim 7 , wherein the output load comprises a transformer winding.
9. The circuitry of claim 8 , wherein:
the output load further comprises a switch connected in series with a catch diode;
the switch and the catch diode are connected in parallel with the transformer winding; and
the switch is configured to be selectively controlled to transmit data via the transformer winding.
10. The circuitry of claim 1 , wherein an output load is connected in series between the collector of the p-type transistor and a low-voltage supply rail of the circuitry.
11. The circuitry of claim 1 , wherein an output load is connected in series between the collector of the n-type transistor and a high-voltage supply rail of the circuitry.
12. The circuitry of claim 1 , wherein the emitter of the n-type transistor is directly connected to the emitter of the p-type transistor.
13. The circuitry of claim 1 , wherein the trigger circuit is part of a pulse generator configured to generate current pulses corresponding to the current flowing from the collector of the n-type transistor to the collector of the p-type transistor.
14. The circuitry of claim 13 , wherein the pulse generator is a controlled pulse generator configured to receive a control signal that controls frequency of the current pulses.
15. The circuitry of claim 13 , wherein the pulse generator is a demand pulse generator on the secondary side of an isolated power converter.
16. The circuitry of claim 15 , wherein the circuitry comprises the isolated power converter configurable to drive an output load.
17. The circuitry of claim 16 , wherein the circuitry comprises the output load.
18. The circuitry of claim 1 , wherein the trigger circuit is part of an oscillator that oscillates with the two transistors repeatedly turning on and off together.
19. The circuitry of claim 18 , wherein the oscillator is a controlled oscillator configured to receive a control signal that controls frequency of the oscillation.
20. The circuitry of claim 1 , wherein the trigger circuit is part of a delay circuit that receives an input signal and generates a delayed output signal when the two transistors turn on together.
21. The circuitry of claim 20 , wherein the delay circuit is a controlled delay circuit configured to receive a control signal that controls magnitude of the delay between the input signal and the delayed output signal.
22. The circuitry of claim 1 , wherein the trigger circuit is part of an edge accelerator that receives an input signal having an input leading edge with an input transition time and generates, when the two transistors turn on together, an output signal having an output leading edge with an output transition time that is shorter than the input transition time.
23. The circuitry of claim 22 , wherein the edge accelerator is a buffer comprising the trigger circuit connected in parallel with a complementary version of the trigger circuit such that:
when the buffer receives a first input signal, the two transistors of the trigger circuit turn on together and the buffer generates an output signal having a first logical value; and
when the buffer receives a second input signal, the two transistors of the complementary version of the trigger circuit turn on together and the buffer generates the output signal having a second logical value.