High-speed 4:1 multiplexer for voltage-mode transmitter with automatic phase alignment technique
A multiphase serialization system for a voltage-mode transmitter includes a N-to-one stage driven by a N-phase input clock, a phase alignment unit driven by the N-phase input clock being operated to generated interpolated sampling clock signals by adjusting a plurality of reference clock signals provided to the phase alignment unit based on the N-phase input clock, and a preceding multiplexing stage driven by the interpolated sampling clock signals configured to receive incoming data streams and to output phase aligned data streams to the N-to-one stage.
1. A multiphase serialization system for a voltage-mode transmitter comprising:
a N-to-one stage driven by a N-phase input clock signals, N being a positive even number;
a phase alignment unit driven by the N-phase input clock signals being configured to generate interpolated sampling clock signals by adjusting a plurality of reference clock signals provided to the phase alignment unit based on the N-phase input clock signals; and
a preceding multiplexing stage driven by the interpolated sampling clock signals configured to receive incoming data streams and to output phase-aligned data streams to the N-to-one stage, wherein the output phase-aligned data streams are aligned with a rising edge of one of the N-phase input clock signals.
2. The system of claim 1 , wherein the preceding multiplexing stage is composed of a plurality of sub-preceding multiplexing stages, each sub-preceding multiplexing stage being driven by the interpolated sampling clock signals is configured to receive the incoming data streams and to output the phase aligned data streams to the N-to-one stage.
3. The system of claim 2 , wherein the phase alignment unit includes:
a first phase interpolator; and
a second phase interpolator coupled to the first phase interpolator,
wherein the first phase interpolator is configured to receive the reference clock signals from the N-phase input clock signals to generate a first interpolated clock signal for driving a portion of the sub-preceding multiplexing stages, and
wherein the second phase interpolator is configured to receive the reference clock signals from the N-phase input clock signals to generate a second interpolated clock signal for driving the remaining portion of the sub-preceding multiplexing stages.
4. The system of claim 3 , wherein the first interpolated clock signal is a zero-degree clock signal.
5. The system of claim 3 , wherein the second interpolated clock signal is a 90-degree clock signal.
6. The system of claim 1 , wherein the alignment of the output phase-aligned data streams is calibrated by checking the states of the one of the N-phase input clock signals at the rising edge of one of the output phase-aligned data streams, if the one of the N-phase input clock signals is high, the phase alignment unit advances the phase of the output phase-aligned data streams letting the phase of the output phase-aligned data streams to catch up the phase of the N-phase input clock signals; if the one of the N-phase input clock signal is low, the phase alignment unit delays the phase of the output phase-aligned data streams letting the phase of the N-phase input clock signals to catch up the phase of the output phase-aligned data streams.
7. The system of claim 1 , wherein the N-to-one stage having N slices, each slice comprises:
a first supply source, a first transistor, a second transistor, and a second supply source serially connected to provide a current path;
a NAND gate coupled to a gate of the first transistor; and
a NOR gate coupled to a gate of the second transistor,
wherein input terminals of the NAND gate or the NOR gate are used for either inputting the phase-aligned data streams or the N-phase input clock signals.
8. The system of claim 7 , wherein the first transistor is a p-type metal-oxide-semiconductor (PMOS) field effect transistor.
9. The system of claim 7 , wherein the second transistor is a n-type metal-oxide-semiconductor (NMOS) field effect transistor.
10. The system of claim 7 , wherein the second supply source is set to be a ground source.
11. A method of multiphase serialization for a voltage-mode transmitter comprising:
providing a N-to-one stage driven by N-phase input clock signals, N being a positive even number;
providing a phase alignment unit driven by the N-phase input clock signals for generating interpolated sampling clock signals by adjusting a plurality of reference clock signals provided to the phase alignment unit based on the N-phase input clock signals; and
providing a preceding multiplexing stage driven by the interpolated sampling clock signals for receiving incoming data streams and outputting phase aligned data streams to the N-to-one stage, wherein the output phase-aligned data streams are aligned with a rising edge of one of the N-phase input clock signals.
12. The method of claim 11 , wherein the preceding multiplexing stage is composed of a plurality of sub-preceding multiplexing stages, each sub-preceding multiplexing stage being driven by the interpolated sampling clock signals is configured to receive the incoming data streams and to output the phase aligned data streams to the N-to-one stage.
13. The method of claim 12 , wherein the phase alignment unit includes:
a first phase interpolator; and
a second phase interpolator coupled to the first phase interpolator,
wherein the first phase interpolator is configured to receive the reference clock signals from the N-phase input clock signals to generate a first interpolated clock signal for driving a portion of the sub-preceding multiplexing stages, and
wherein the second phase interpolator is configured to receive the reference clock signals from the N-phase input clock signals to generate a second interpolated clock signals for driving the remaining portion of the sub-preceding multiplexing stages.
14. The method of claim 13 , wherein the first interpolated clock signal is a zero-degree clock signal.
15. The method of claim 13 , wherein the second interpolated clock signal is a 90-degree clock signal.
16. The method of claim 11 , wherein the alignment of the output phase-aligned data streams is calibrated by checking the states of the one of the N-phase input clock signals at the rising edge of one of the output phase-aligned data streams, if the one of the N-phase input clock signals is high, the phase alignment unit advances the phase of the output phase-aligned data streams letting the phase of the output phase-aligned data streams to catch up the phase of the N-phase input clock signals; if the one of the N-phase input clock signals is low, the phase alignment unit delays the phase of the output phase-aligned data streams letting the phase of the N-phase input clock signals to catch up the phase of the output phase-aligned data streams.
17. The method of claim 11 , wherein the N-to-one stage having N slices, each slice comprises:
a first supply source, a first transistor, a second transistor, and a second supply source serially connected to provide a current path;
a NAND gate coupled to a gate of the first transistor; and
a NOR gate coupled to a gate of the second transistor,
wherein input terminals of the NAND gate or the NOR gate are used for either inputting the phase-aligned data streams or the N-phase input clock signals.
18. The method of claim 17 , wherein the first transistor is a p-type metal-oxide-semiconductor (PMOS) field effect transistor.
19. The method of claim 17 , wherein the second transistor is a n-type metal-oxide-semiconductor (NMOS) field effect transistor.
20. The method of claim 17 , wherein the second supply source is set to be a ground source.