Systems and methods to generate a test bench for electrostatic discharge analysis of an integrated circuit design

1. A computer implemented method comprising:

receiving, by a computer, a netlist file comprising data records of a plurality of circuit devices and a plurality of nets interconnecting the plurality of circuit devices, wherein the netlist file forms a device under test (DUT);

calculating, by the computer, a first parameter associated with a first injection pin of the DUT based upon data records of at least a first portion of the plurality of circuit devices and the plurality of nets;

generating, by the computer, a first test bench comprising a resistance inductance capacitance (RLC) circuit for the first injection pin based on the first parameter;

transmitting, by the computer, an electrostatic discharge (ESD) stimulus from the RLC circuit to the first injection pin of the DUT;

in response to determining by the computer that the ESD stimulus discharged through a ground pin of the DUT:

generating, by the computer, an indication that the DUT has passed an ESD analysis test on the first injection pin; and

generating, by the computer, a second test bench comprising a second RLC circuit for the second injection pin based on a second parameter associated with a second injection pin of the DUT.

2. The method of claim 1 , further comprising:

displaying, by the computer, the indication that the DUT has passed the ESD analysis test on the first injection pin on a graphical user interface.

3. The method of claim 1 , wherein the first parameter comprises at least one of: an ON resistance of the first injection pin and characteristics of the substrate network of the DUT.

4. The method of claim 1 , further comprising:

receiving, by the computer, a selection of the second injection pin and a second ground pin;

calculating, by the computer, the second parameter associated with the second injection pin of the DUT based upon data records of at least a second portion of the plurality of circuit devices and the plurality of nets;

transmitting, by the computer, a second ESD stimulus from the second RLC circuit to the second injection pin of the DUT; and

in response to determining by the computer that the second ESD stimulus discharged through the second ground pin of the DUT:

generating, by the computer, an indication that the DUT has passed an ESD analysis test on the second injection pin.

5. The method of claim 1 , further comprising:

receiving, by the computer, a selection of the first injection pin and the ground pin.

6. The method of claim 1 , wherein at least one test bench is based upon a human body model or charged device model.

7. The method of claim 1 , wherein a package circuit is connected to the DUT.

8. The method of claim 1 , further comprising:

receiving, by the computer, a selection of human body model or a charged device model through a graphical user interface; and

generating, by the computer, the at least one test bench based upon the received selection.

9. The method of claim 1 , further comprising:

displaying, by the computer, a graphical user interface configured to allow a modification of the ESD stimulus.

10. A system for circuit design, comprising:

one or more computers comprising a non-transitory machine-readable media configured to store a netlist file comprising data records of a plurality of circuit devices and a plurality of nets interconnecting the plurality of circuit devices, wherein the netlist file forms a device under test (DUT);

at least one computer of the one or more computers, the at least one computer coupled to the non-transitory machine readable media storing the netlist file and comprising a processor configured to:

calculate a plurality of parameters associated respectively with a plurality of injection pins of the DUT based upon data records of at least a corresponding portion of the plurality of circuit devices and the plurality of nets;

generate a plurality of pin-specific test benches, including a first test bench comprising a first resistance inductance capacitance (RLC) circuit for a first injection pin based on a first parameter and a second test bench comprising a second RLC circuit for a second injection pin based on a second parameter;

transmit an electrostatic discharge (ESD) stimulus from the RLC circuit to the first injection pin of the DUT; and

in response to determining by the processor that the ESD stimulus discharged through a ground pin of the DUT:

generate an indication that the DUT has passed an ESD analysis test on the first injection pin.

11. The system of claim 10 , wherein the processor is further configured to:

displaying, by the computer, the indication that the DUT has passed the ESD analysis test on the first injection pin on a graphical user interface.

12. The system of claim 10 , wherein first parameter comprises at least one of: an ON resistance of the first injection pin and characteristics of the substrate network of the DUT.

13. The system of claim 10 , wherein the processor is further configured to:

receive a selection of the second injection pin and a second ground pin;

calculate the second parameter associated with the second injection pin of the DUT based upon data records of at least a second corresponding portion of the plurality of circuit devices and the plurality of nets;

transmit a second ESD stimulus from the second RLC circuit to the second injection pin of the DUT; and

in response to determining by the processor that the second ESD stimulus discharged through the second ground pin of the DUT:

generate an indication that the DUT has passed an ESD analysis test on the injection second pin.

14. The system of claim 10 , wherein the processor is further configured to:

receive a selection of the first injection pin and the ground pin.

15. The system of claim 10 , wherein at one test bench is based upon a human body model or a charged device model.

16. The system of claim 10 , wherein a package circuit is connected to the DUT.

17. The system of claim 10 , wherein the processor is further configured to:

receive a selection of human body model or a charged device model through a graphical user interface; and

generate at least one test bench based upon the received selection.

18. The system of claim 10 , wherein the processor is further configured to:

display a graphical user interface configured to allow a modification of the ESD stimulus.

19. A computer readable non-transitory medium containing one or more computer instructions, which when executed by a processor cause the processor to:

receive a netlist file comprising data records of a plurality of circuit devices and a plurality of nets interconnecting the plurality of circuit devices, wherein the netlist file forms a device under test (DUT);

calculate a first parameter associated with a first injection pin of the DUT based upon data records of at least a portion of the plurality of circuit devices and the plurality of nets;

generate a first test bench comprising a resistance inductance capacitance (RLC) circuit for the first injection pin based on the first parameter;

transmit an electrostatic discharge (ESD) stimulus from the RLC circuit to the first injection pin of the DUT;

in response to determining by the processor that the ESD stimulus discharged through a ground pin of the DUT:

generate an indication that the DUT has passed an ESD analysis test on the first injection pin; and

generate a second test bench comprising a second RLC circuit for the second injection pin based on a second parameter associated with a second injection pin of the DUT.

20. The computer readable non-transitory medium of claim 19 , comprising further instructions to cause the processor to:

display the indication that the DUT has passed the ESD analysis test on the first injection pin on a graphical user interface.