Secured chip

1. A method of individualizing a semiconductor chip of a batch of semiconductor chips with respective individualization data of the semiconductor chip, the method comprising:

applying a plurality of circuit layouts to the semiconductor chip to form a plurality of circuits on the semiconductor chip,

wherein for each circuit layout:

said circuit layout is arranged such that:

(a) the corresponding circuit, when triggered, falls into any one of two or more respective triggered states, and

(b) one of the two or more respective triggered states is a respective preferred state defined by said circuit layout,

wherein the plurality of respective preferred states of the circuits in the plurality of circuits encode the individualization data, and wherein each individualized semiconductor chip of the batch of semiconductor chips comprises a generic circuit; and

wherein for one or more circuit layouts each circuit layout comprises two or more respective variant sub-circuit layouts, each respective sub-circuit layout corresponding to a respective triggered state of the circuit corresponding to the circuit layout.

2. The method of claim 1 , wherein the plurality of respective preferred states of the circuits in the plurality of circuits encode the individualization data using an error correcting code.

3. The method of claim 1 , wherein for each of the one or more circuit layouts:

one of the respective variant sub-circuit layouts comprises a circuit layout variation with respect to the other ones respective variant sub-circuit layouts, wherein the circuit layout variation comprises any of, a dimension of a functional element, a position shift of a functional element, and a characteristic of a functional element.

4. The method of claim 3 , wherein the functional element comprises any of:

a gate;

a source;

a drain;

a well;

a resistor;

a capacitor; and

a connection.

5. The method of claim 4 , wherein the generic circuit was formed on the semiconductor chip using a coarser resolution, wherein the a circuit layout variation defines a difference of the variant sub-circuit formed by applying the one of the respective variant sub-circuit with respect to the variant sub-circuits formed by applying the other ones respective variant sub-circuit layouts that cannot be resolved at the coarser resolution.

6. The method of claim 1 , wherein the at least one circuit layout is applied using a beam steered lithographic process with a finer resolution, and

the generic circuit is formed on the semiconductor chip using a mask based lithographic process.

7. The method of claim 1 , wherein the individualization data comprises one or more cryptographic keys.

8. The method of claim 1 , wherein the individualization data comprises one or more enablement vectors specifying the functionality of the generic circuit available to the individualized semiconductor chip.

9. The method of claim 1 , wherein any of the circuit layouts comprise a respective obfuscated circuit layout.

10. A batch of individualized semiconductor chips, each individualized semiconductor chip comprising:

a generic circuit; and

a respective individualized plurality of circuits,

wherein for each circuit of the respective plurality:

said circuit corresponds to a respective circuit layout which is arranged such that:

(a) the corresponding circuit, when triggered, falls into any one of two or more respective triggered states, and

(b) one of the two or more respective triggered states is a respective preferred state defined by said circuit layout,

wherein the respective individualized plurality of respective preferred states encode respective individualization data; and

wherein for one or more circuit layouts each circuit layout comprises two or more respective variant sub-circuit layouts, each respective sub-circuit layout corresponding to a respective triggered state of the circuit corresponding to the circuit layout.

11. A method of securely embedding a circuit on a semiconductor wafer to form a reverse engineering resistant semiconductor chip, wherein the method uses a first lithographic process, and a second lithographic process, wherein the first lithographic process has a first characteristic resolution corresponding to a set of coarser resolutions and the second lithographic process has a second characteristic resolution corresponding to a set of finer resolutions, the method comprising:

(a) for one or more layers of the semiconductor chip:

applying a respective circuit layout from a first set of circuit layouts to said layer using a first lithographic process at a respective coarser resolution from the set of coarser resolutions, to form a respective circuit at said respective coarser resolution,

(b) for one layer of the semiconductor chip:

applying a circuit layout to said layer using a second lithographic process at a respective finer resolution from the set of finer resolutions, to form the securely embedded circuit at said respective finer resolution, and wherein said circuit layout defines a set of functional elements in said securely embedded circuit that cannot be resolved at the respective coarser resolution of the set of coarser resolutions.

12. The method of claim 11 , wherein the circuit layout defines a set of functional elements in said securely embedded circuit that cannot be resolved at any of the coarser resolutions of the set of coarser resolutions.

13. The method of claim 11 , wherein the one layer of step (b) is one of the one or more layers of step (a), such that the one layer of step (b) comprises both the respective circuit at said respective coarser resolution and the securely embedded circuit at said respective finer resolution.

14. The method of claim 11 , wherein the one layer of the semiconductor chip comprises the base layer.

15. The method of claim 11 , wherein the securely embedded circuit uses one or more connections of a circuit in a higher layer.

16. The method of claim 11 , wherein the first lithographic process comprises a mask based lithographic process, and

the second lithographic process comprises a beam steered lithographic process.