Clock network analysis using harmonic balance

1. A computer-implemented method of performing clock network analysis of a clock network of an integrated circuit that includes a grid, the method comprising:

obtaining parameters for each transmission line of the clock network that carries a clock signal between a source of the clock signal and the grid, wherein the obtaining the parameters includes obtaining resistance R, inductance L, capacitance C, conductance G, and line length d;

obtaining models of nonlinear components of the clock network;

numerically solving, using a processor, a frequency domain nonlinear Harmonic Balance equation to obtain voltage values at an input and an output of each of the nonlinear components, wherein a number of the voltage values obtained is proportional to the number of the nonlinear components, wherein the numerically solving the Harmonic Balance equation includes iteratively evaluating the models of the nonlinear components for a candidate voltage value; and

obtaining a physical implementation of the integrated circuit based on the clock network analysis.

2. The computer-implemented method according to claim 1 , further comprising obtaining other voltage values associated with linear components of the clock network based on the voltage values.

3. The computer-implemented method according to claim 1 , further comprising obtaining current values corresponding with the voltage values, wherein the voltage values and the current values represent clock signal waveforms for the clock network analysis and the clock network analysis includes determining timing, undershoot, and overshoot.

4. The computer-implemented method according to claim 1 , wherein the obtaining the models includes obtaining transistor-level current source models of buffers.

5. The computer-implemented method according to claim 1 , wherein the numerically solving the Harmonic Balance equation includes using the parameters of the transmission line respective to the nonlinear component.

6. A system to perform clock network analysis of a clock network of an integrated circuit that includes a grid, the system comprising:

a memory device configured to store parameters for each transmission line of the clock network that carries a clock signal between a source of the clock signal and the grid and models of nonlinear components of the clock network, wherein the parameters include resistance R, inductance L, capacitance C, conductance G, and line length d; and

a processor configured to numerically solve a frequency domain nonlinear Harmonic Balance equation to obtain voltage values at an input and an output of each of the nonlinear components, wherein a number of the voltage values obtained is limited by the number of the nonlinear components and the clock network analysis is used to obtain a physical implementation of the integrated circuit, wherein the processor numerically solves the Harmonic Balance equation by iteratively evaluating the models of the nonlinear components for a candidate voltage value.

7. The system according to claim 6 , wherein the processor is further configured to obtain other voltage values associated with linear components of the clock network based on the voltage values.

8. The system according to claim 6 , wherein the processor is further configured to obtain current values corresponding with the voltage values, wherein the voltage values and the current values represent clock signal waveforms for the clock network analysis and the clock network analysis includes determining timing, undershoot, and overshoot.

9. The system according to claim 6 , wherein the models include transistor-level current source models of buffers.

10. The system according to claim 6 , wherein the processor numerically solves the Harmonic Balance equation by using the parameters of the transmission line respective to the nonlinear component.

11. A non-transitory computer program product for performing clock network analysis of a clock network of an integrated circuit that includes a grid, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to perform a method comprising:

obtaining parameters for each transmission line of the clock network that carries a clock signal between a source of the clock signal and the grid, wherein the obtaining the parameters includes obtaining resistance R, inductance L, capacitance C, conductance G, and line length d;

obtaining models of nonlinear components of the clock network;

numerically solving a frequency domain nonlinear Harmonic Balance equation to obtain voltage values at an input and an output of each of the nonlinear components, wherein a number of the voltage values obtained is proportional to the number of the nonlinear components, wherein the numerically solving the Harmonic Balance equation includes iteratively evaluating the models of the nonlinear components for a candidate voltage value; and

obtaining a physical implementation of the integrated circuit based on the clock network analysis.

12. The computer program product according to claim 11 , further comprising obtaining other voltage values associated with linear components of the clock network based on the voltage values.

13. The computer program product according to claim 11 , further comprising obtaining current values corresponding with the voltage values, wherein the voltage values and the current values represent clock signal waveforms for the clock network analysis and the clock network analysis includes determining timing, undershoot, and overshoot.

14. The computer program product according to claim 11 , wherein the obtaining the models includes obtaining transistor-level current source models of buffers.

15. The computer program product according to claim 11 , wherein the numerically solving the Harmonic Balance equation includes using the parameters of the transmission line respective to the nonlinear component.