IP Library › Granted Patent US 10,620,850
Granted Patent B1
US 10,620,850 · App. 15/086,390 · Granted Apr 14, 2020

Caching techniques duplicating dirty data in secondary cache

Inventors: Xinlei Xu (Beijing, CN); Liam Xiongcheng Li (Beijing, CN); Lifeng Yang (Beijing, CN); Jian Gao (Beijing, CN); Lili Chen (Hopkinton, MA); Ruiyong Jia (Beijing, CN)
Assignee: EMC IP Holding Company LLC
G06F3/0619G06F3/067G06F3/0644G06F3/0656G06F3/0689G06F12/084G06F12/0893G06F12/0897G06F2212/1032G06F2212/621
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Quick Facts
Patent No.
US 10,620,850
App. No.
15/086,390
Filed
Mar 31, 2016
Granted
Apr 14, 2020
Kind
B1
Art Unit
2139
USPC
711/120
Abstract

Described are techniques for data caching. Dirty cached data of a first logical address may be stored in a secondary cache included in multiple caching layers. The multiple caching layers may also include a primary data cache. Two copies of the dirty cached data may be stored in two different cache pages on two different physical devices of the secondary cache. The two cache pages may be marked as dirty indicating that data stored in the cache pages of the secondary cache is a more recent copy of data stored at the first logical address than other data stored on first non-volatile physical storage. Clean cached data of a second logical address may also be stored in the secondary cache where a single copy of the clean cached data is stored in physical storage of the secondary cache.

Claims (79)

1. A method of caching data comprising:

receiving a first write operation that writes first data to a first logical address;

storing the first data of the first write operation in a primary data cache, wherein the primary data cache and a secondary cache are included in a plurality of caching layers;

performing processing to destage the first data, located in the primary data cache with a status of dirty, from the primary data cache to non-volatile physical storage comprising:

determining, for the first logical address, that includes the first data stored in the primary data cache being destaged to non-volatile physical storage, whether a frequency of access of the first logical address exceeds a threshold level; and

responsive to determining that the first logical address, that includes the first data stored in the primary data cache being destaged to non-volatile physical storage, has a frequency exceeding the threshold level, performing first processing including:

storing the first data, located in the primary data cache with the status of dirty, from the primary data cache into the secondary cache as dirty cached data of the first logical address, wherein a first copy of the dirty cached data is stored in a first cache page on a first physical device of the secondary cache and a second copy of the dirty cached data is stored in a second cache page on a second physical device of the secondary cache, said first physical device and said second physical device being different physical devices, said first cache page and said second cache page each being marked as dirty indicating that data stored in said each cache page of the secondary cache is a more recent copy of data stored at the first logical address than other data stored on first non-volatile physical storage;

storing either the first copy of the dirty cached data or the second copy of the dirty cached data from the secondary cache to the first non-volatile storage; and

responsive to storing either the first copy of the dirty cached data or the second copy of the dirty cached data from the secondary cache to the first non-volatile storage, updating the status of the first data in the primary data cache from dirty to clean indicating that the first data stored in the primary data cache is synchronized with the first non-volatile storage providing back-end physical storage mapped to the first logical address; and

storing clean cached data of a second logical address in the secondary cache, wherein a single copy of the clean cached data is stored in a third cache page on physical storage of the secondary cache.

2. The method of claim 1 , wherein the clean cached data is synchronized with data stored on second non-volatile physical storage providing back-end physical storage mapped to the second logical address.

3. The method of claim 1 , wherein said first non-volatile storage is back-end physical storage that includes a physical storage portion mapped to the first logical address, and wherein said first non-volatile storage is not included in any of the plurality of caching layers.

4. The method of claim 1 , wherein the first processing further comprises:

storing the first copy of the dirty cached data from the secondary cache to the first non-volatile storage; and

responsive to storing the first copy of the dirty cached data from the secondary cache to the first non-volatile storage, performing second processing including:

removing the second copy of the dirty cached data;

marking the second cache page storing the second copy as free and available for storing other cached data of the secondary cache; and

marking the first copy of the dirty data cached data as clean cached data indicating that the first cache page includes data synchronized with data stored on a portion of the first non-volatile storage providing back-end physical storage that is mapped to the first logical address.

5. The method of claim 1 , wherein a cache hit is determined with respect to the secondary cache when an I/O operation directed to a logical address has its data stored in the secondary cache.

6. The method of claim 1 , wherein a cache miss is determined with respect to the secondary cache when an I/O operation directed to a logical address does not have its data stored in the secondary cache.

7. The method of claim 1 , further comprising:

receiving a write operation that stores first write data to the second logical address;

storing the first write data in the primary data cache;

performing processing to destage the first write data of the second logical address comprising:

determining whether there is a cache hit with respect to the secondary cache for the second logical address; and

responsive to determining there is a cache hit with respect to the secondary cache for the second logical address, performing second processing comprising:

storing the first write data in the third cache page;

storing the first write data in a fourth cache page of the secondary cache, wherein said third cache page and said fourth cache page are each on a different physical storage device of the secondary cache;

marking the first write data stored in the third cache page and the fourth cache page as second dirty cached data indicating that the first write data stored in the third and the fourth cache pages of the secondary cache is a more recent copy of data stored at second logical address than other data stored on second non-volatile physical storage providing back-end physical storage mapped to the second logical address.

8. The method of claim 1 , wherein the secondary cache is a flash disk cache including a plurality of flash-based storage devices.

9. The method of claim 8 , wherein the first physical device including the first copy of the dirty cached data is a first of the plurality of flash-based storage devices, and the second physical device including the second copy of the dirty cached data is a second of the plurality of flash-based devices different from the first flash-based storage device.

10. The method of claim 1 , wherein each cache page of the secondary cache stores an amount of data denoted by a first amount, and wherein the method further comprises:

receiving a second write operation that writes second data to a target logical address;

determining whether the second data has a size larger than the first amount;

responsive to determining the second data has a size larger than the first amount, partitioning the second write operation into a plurality of write operations each writing a different portion of the second data wherein said different portion has a size that is equal to or less than the first amount; and

processing each of the plurality of write operations and, for each of said plurality of write operations, determining whether to cache a portion of the second data, as written by said each write operation, in the secondary cache.

11. The method of claim 1 , further comprising:

receiving write data to store in the secondary cache;

determining that there are no free pages in the secondary cache;

responsive to determining there are no free pages in the secondary cache, selecting a particular cache page of the secondary cache wherein the particular cache page includes clean cache data synchronized with the first non-volatile storage; and

storing the write data to the selected particular cache page.

12. The method of claim 11 , wherein said selecting selects the particular cache page in accordance with an age associated with current data stored in the particular cache page prior to storing the write data.

13. The method of claim 12 , wherein the particular cache page is a least recently used cache page of a plurality of cache pages.

14. A non-transitory computer readable medium comprising code stored thereon that, when executed, performs a method of caching data comprising:

receiving a first write operation that writes first data to a first logical address;

storing the first data of the first write operation in a primary data cache, wherein the primary data cache and a secondary cache are included in a plurality of caching layers;

performing processing to destage the first data, located in the primary data cache with a status of dirty, from the primary data cache to non-volatile physical storage comprising:

determining, for the first logical address, that includes the first data stored in the primary data cache being destaged to non-volatile physical storage, whether a frequency of access of the first logical address exceeds a threshold level; and

responsive to determining that the first logical address, that includes the first data stored in the primary data cache being destaged to non-volatile physical storage, has a frequency exceeding the threshold level, performing first processing including:

storing the first data, located in the primary data cache with the status of dirty, from the primary data cache into the secondary cache as dirty cached data of the first logical address, wherein a first copy of the dirty cached data is stored in a first cache page on a first physical device of the secondary cache and a second copy of the dirty cached data is stored in a second cache page on a second physical device of the secondary cache, said first physical device and said second physical device being different physical devices, said first cache page and said second cache page each being marked as dirty indicating that data stored in said each cache page of the secondary cache is a more recent copy of data stored at the first logical address than other data stored on first non-volatile physical storage;

storing either the first copy of the dirty cached data or the second copy of the dirty cached data from the secondary cache to the first non-volatile storage; and

responsive to storing either the first copy of the dirty cached data or the second copy of the dirty cached data from the secondary cache to the first non-volatile storage, updating the status of the first data in the primary data cache from dirty to clean indicating that the first data stored in the primary data cache is synchronized with the first non-volatile storage providing back-end physical storage mapped to the first logical address; and

storing clean cached data of a second logical address in the secondary cache, wherein a single copy of the clean cached data is stored in a third cache page on physical storage of the secondary cache.

15. The method of claim 1 , wherein said processing to destage the first data from the primary data cache to non-volatile physical storage further includes:

responsive to determining the first logical address, that includes the first data stored in the primary data cache being destaged to non-volatile storage, does not have a frequency of access exceeding the threshold level, writing the first data of the first logical address directly from the primary data cache to the first non-volatile storage without storing the first data of the first logical device in the secondary cache.

16. The method of claim 1 , wherein processing of a read miss operation to obtain read data includes:

determining that the read data is not stored in the primary data cache and not stored in the secondary cache;

reading the read data from non-volatile physical storage; and

storing the read data in the primary data cache and not storing the read data in the secondary data cache.

17. The non-transitory computer readable medium of claim 14 , wherein the clean cached data is synchronized with data stored on second non-volatile physical storage providing back-end physical storage mapped to the second logical address.

18. The non-transitory computer readable medium of claim 14 , wherein said first non-volatile storage is back-end physical storage that includes a physical storage portion mapped to the first logical address, and wherein said first non-volatile storage is not included in any of the plurality of caching layers.

19. The non-transitory computer readable medium of claim 14 , wherein the first processing further comprises:

storing the first copy of the dirty cached data from the secondary cache to the first non-volatile storage; and

responsive to storing the first copy of the dirty cached data from the secondary cache to the first non-volatile storage, performing second processing including:

removing the second copy of the dirty cached data;

marking the second cache page storing the second copy as free and available for storing other cached data of the secondary cache; and

marking the first copy of the dirty data cached data as clean cached data indicating that the first cache page includes data synchronized with data stored on a portion of the first non-volatile storage providing back-end physical storage that is mapped to the first logical address.

20. A system comprising:

one or more processors; and

a memory comprising code stored thereon that, when executed by at least a first of the one or more processors, performs a method of caching data comprising:

receiving a first write operation that writes first data to a first logical address;

storing the first data of the first write operation in a primary data cache, wherein the primary data cache and a secondary cache are included in a plurality of caching layers;

performing processing to destage the first data, located in the primary data cache with a status of dirty, from the primary data cache to non-volatile physical storage comprising:

determining, for the first logical address, that includes the first data stored in the primary data cache being destaged to non-volatile physical storage, whether a frequency of access of the first logical address exceeds a threshold level; and

responsive to determining that the first logical address, that includes the first data stored in the primary data cache being destaged to non-volatile physical storage, has a frequency exceeding the threshold level, performing first processing including:

storing the first data, located in the primary data cache with the status of dirty, from the primary data cache into the secondary cache as dirty cached data of the first logical address, wherein a first copy of the dirty cached data is stored in a first cache page on a first physical device of the secondary cache and a second copy of the dirty cached data is stored in a second cache page on a second physical device of the secondary cache, said first physical device and said second physical device being different physical devices, said first cache page and said second cache page each being marked as dirty indicating that data stored in said each cache page of the secondary cache is a more recent copy of data stored at the first logical address than other data stored on first non-volatile physical storage;

storing either the first copy of the dirty cached data or the second copy of the dirty cached data from the secondary cache to the first non-volatile storage; and

responsive to storing either the first copy of the dirty cached data or the second copy of the dirty cached data from the secondary cache to the first non-volatile storage, updating the status of the first data in the primary data cache from dirty to clean indicating that the first data stored in the primary data cache is synchronized with the first non-volatile storage providing back-end physical storage mapped to the first logical address; and

storing clean cached data of a second logical address in the secondary cache, wherein a single copy of the clean cached data is stored in a third cache page on physical storage of the secondary cache.

Assignments (10)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053546/0001) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC IP HOLDING COMPANY LLC
Reel/Frame 071642/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (045455/0001) Recorded May 20, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO ASAP SOFTWARE EXPRESS, INC.); DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL USA L.P.; DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC CORPORATION (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO MAGINATICS LLC); EMC IP HOLDING COMPANY LLC (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO MOZY, INC.); SCALEIO LLC
Reel/Frame 061753/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (040136/0001) Recorded Apr 26, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO ASAP SOFTWARE EXPRESS, INC.); DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL USA L.P.; DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC CORPORATION (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO MAGINATICS LLC); EMC IP HOLDING COMPANY LLC (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO MOZY, INC.); SCALEIO LLC
Reel/Frame 061324/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 3, 2021
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: ASAP SOFTWARE EXPRESS, INC.; AVENTAIL LLC; CREDANT TECHNOLOGIES, INC.; DELL USA L.P.; DELL INTERNATIONAL, L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL SOFTWARE INC.; DELL SYSTEMS CORPORATION; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; FORCE10 NETWORKS, INC.; MAGINATICS LLC; MOZY, INC.; SCALEIO LLC; WYSE TECHNOLOGY L.L.C.
Reel/Frame 058216/0001 →
SECURITY AGREEMENT Recorded Apr 22, 2020
From: CREDANT TECHNOLOGIES INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 053546/0001 →
SECURITY AGREEMENT Recorded Mar 21, 2019
From: CREDANT TECHNOLOGIES, INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 049452/0223 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 29, 2016
From: EMC CORPORATION
To: EMC IP HOLDING COMPANY LLC
Reel/Frame 040203/0001 →
SECURITY AGREEMENT Recorded Sep 21, 2016
From: ASAP SOFTWARE EXPRESS, INC.; AVENTAIL LLC; CREDANT TECHNOLOGIES, INC.; DELL USA L.P.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL SOFTWARE INC.; DELL SYSTEMS CORPORATION; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; FORCE10 NETWORKS, INC.; MAGINATICS LLC; MOZY, INC.; SCALEIO LLC; SPANNING CLOUD APPS LLC; WYSE TECHNOLOGY L.L.C.
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 040136/0001 →
SECURITY AGREEMENT Recorded Sep 21, 2016
From: ASAP SOFTWARE EXPRESS, INC.; AVENTAIL LLC; CREDANT TECHNOLOGIES, INC.; DELL USA L.P.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL SOFTWARE INC.; DELL SYSTEMS CORPORATION; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; FORCE10 NETWORKS, INC.; MAGINATICS LLC; MOZY, INC.; SCALEIO LLC; SPANNING CLOUD APPS LLC; WYSE TECHNOLOGY L.L.C.
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH, AS COLLATERAL AGENT
Reel/Frame 040134/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 31, 2016
From: XU, XINLEI; LI, LIAM XIONGCHENG; YANG, LIFENG; GAO, JIAN; CHEN, LILI; JIA, RUIYONG
To: EMC CORPORATION
Reel/Frame 038153/0828 →
Cited By (2)
US 12,367,151 US 12,505,045