Routing circuit designs for implementation using a programmable network on chip

1. A method for routing a circuit design for implementation in an integrated circuit having a programmable network on chip, the method comprising:

determining Quality of Service (QOS) parameters for data flows of a circuit design, wherein the data flows involve transfers of data between masters and slaves through the programmable network on chip;

generating, using a processor, an expression having a plurality of variables representing the data flows, routing constraints, and the QOS parameters;

determining, using the processor, a routing solution for the data flows of the circuit design by initiating execution of a SAT solver using the expression; and

wherein the constraints include directionality constraints requiring that data flows having a same destination, that have a shared switch of the programmable network on chip, and are assigned a same virtual channel use a same path through the programmable network on chip from the shared switch to the destination.

2. The method of claim 1 , wherein the programmable network on chip is configured to implement routes for the data flows specified by the routing solution in response to, or after, booting the integrated circuit.

3. The method of claim 1 , wherein the programmable network on chip comprises a plurality of interconnected switches, wherein the programmable network on chip is configured by programming routing tables of the plurality of switches to establish the routes.

4. The method of claim 1 , wherein the QOS parameters include at least one of bandwidth, traffic class, communication type, or maximal latency.

5. The method of claim 1 , wherein the constraints include conductive constraints specifying that a path between the master and the slave of each data flow exists.

6. The method of claim 1 , wherein the constraints include physical capacity constraints specifying that total bandwidth of data flows going through switches of the programmable network on chip remains less than or equal to capacities of the switches.

7. The method of claim 1 , wherein the constraints include virtual channel constraints specifying that each data flow uses one virtual channel.

8. The method of claim 7 , wherein the virtual channel constraints specify that data flows in a same group must use a compatible virtual channel.

9. The method of claim 1 , wherein the constraints include deadlock avoidance constraints that enforce acyclicity of a directed graph for each virtual channel.

10. A system for routing a circuit design for implementation in an integrated circuit having a programmable network on chip, comprising:

a memory configured to store program code; and

a processor coupled to the memory, wherein the processor, in response to executing the program code, is configured to initiate operations including:

determining Quality of Service (QOS) parameters for data flows of a circuit design, wherein the data flows involve transfers of data between masters and slaves through the programmable network on chip;

generating, using a processor, an expression having a plurality of variables representing the data flows, routing constraints, and the QOS parameters;

determining, using the processor, a routing solution for the data flows of the circuit design by initiating execution of a SAT solver using the expression; and

wherein the constraints include directionality constraints requiring that data flows having a same destination, that have a shared switch of the programmable network on chip, and are assigned a same virtual channel use a same path through the programmable network on chip from the shared switch to the destination.

11. The system of claim 10 , wherein the programmable network on chip is configured to implement routes for the data flows specified by the routing solution in response to, or after, booting the integrated circuit.

12. The system of claim 10 , wherein the programmable network on chip comprises a plurality of interconnected switches, wherein the programmable network on chip is configured by programming routing tables of the plurality of switches to establish the routes.

13. The system of claim 10 , wherein the QOS parameters include at least one of bandwidth, traffic class, communication type, or maximal latency.

14. The system of claim 10 , wherein the constraints include conductive constraints specifying that a path between the master and the slave of each data flow exists.

15. The system of claim 10 , wherein the constraints include physical capacity constraints specifying that total bandwidth of data flows going through switches of the programmable network on chip remains less than or equal to capacities of the switches.

16. The system of claim 10 , wherein the constraints include virtual channel constraints specifying that each data flow uses one virtual channel.

17. The system of claim 10 , wherein the constraints include deadlock avoidance constraints that enforce acyclicity of a directed graph for each virtual channel.

18. An integrated circuit, comprising:

a processor configured to execute program code;

a programmable circuitry;

a programmable network on chip coupling the processor and the programmable circuitry;

wherein the programmable network on chip is configured, in response to booting the integrated circuit, to implement routes between the processor and the programmable circuitry to convey data flows between masters and slaves of a circuit design; and

wherein selected data flows through the programmable network on chip having a same destination, having a shared switch of the programmable network on chip, and assigned to a same virtual channel use a same path through the programmable network on chip from the shared switch to the destination.