IP Library Granted Patent US 10,629,530
Granted Patent B2
US 10,629,530 · App. 15/479,978 · Granted Apr 21, 2020

Semiconductor device, electrical energy measurement instrument, and manufacturing method of semiconductor device

Inventors: Shinichi Uchida (Kodaira, JP); Keiichiro Tanaka (Kodaira, JP); Takafumi Kuramoto (Kodaira, JP)
Assignee: RENESAS ELECTRONICS CORPORATION
H01L23/5227G01R15/18G01R15/181G01R19/0092H01F17/0013H01F27/2804H01F27/34H01F41/041H01L21/32053H01L21/32055H01L21/76224H01L23/528H01L23/5225H01L23/53209H01L23/53271H01L23/552H01L29/0649H01F2017/008H01F2017/0073H01F2017/0086H01F2027/2809
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Quick Facts
Patent No.
US 10,629,530
App. No.
15/479,978
Granted
Apr 21, 2020
Kind
B2
Abstract

According to one embodiment, a semiconductor device 1 includes an Si substrate 11 , an inductor 12 formed in wiring layers disposed above the Si substrate 11 , and a shield 13 formed so as to surround the inductor 12 , in which the shield 13 includes metals 105 to 109 formed in, among the wiring layers, a layer in which the inductor 12 is formed and a layer above that layer, and a silicide 104 formed between the Si substrate 11 and the wiring layers above the Si substrate 11.

Claims (39)

1. A semiconductor device comprising:

a substrate;

an inductor formed in wiring layers disposed above the substrate; and

a shield formed so as to surround the inductor, wherein the shield comprises:

a first metal formed in, among the wiring layers, a layer in which the inductor is formed and a layer above that layer; and

a silicide formed between the substrate and the wiring layers above the substrate;

wherein the shield further comprises a second metal formed in, among the wiring layers, a wiring layer located between the layer in which the inductor is formed and the silicide in addition to the first metal and the silicide,

wherein the silicide comprises a first gap area in a plan view, and the second metal comprises a second gap area and is disposed so as to cover a part or all of the first gap area of the silicide in the plan view,

wherein

the silicide comprises a plurality of partial silicide pieces arranged in a matrix pattern in the plan view, and

the second metal comprises a plurality of partial metal pieces arranged in a matrix pattern and is disposed so as to cover a part of the first gap area of the silicide in the plan view.

2. A semiconductor device comprising:

a substrate;

an inductor formed in wiring layers disposed above the substrate; and

a shield formed so as to surround the inductor, wherein the shield comprises:

a first metal formed in, among the wiring layers, a layer in which the inductor is formed and a layer above that layer; and

a silicide formed between the substrate and the wiring layers above the substrate;

wherein the shield further comprises a second metal formed in, among the wiring layers, a wiring layer located between the layer in which the inductor is formed and the silicide in addition to the first metal and the silicide,

wherein the silicide comprises a first gap area in a plan view, and the second metal comprises a second gap area and is disposed so as to cover a part or all of the first gap area of the silicide in the plan view,

wherein

the silicide is formed in a grid pattern in the plan view, and

the second metal is formed in a grid pattern and is disposed so as to cover a part of the first gap area of the silicide in the plan view.

3. The semiconductor device according to claim 2 , further comprising a polysilicon formed above the substrate, wherein

the silicide is formed on a surface of the polysilicon.

4. The semiconductor device according to claim 3 , further comprising an STI (Shallow Trench Isolation) formed above the substrate, wherein

the polysilicon is formed on a surface of the STI.

5. The semiconductor device according to claim 2 , further comprising an N-type or P-type diffusion layer formed above the substrate, wherein

the silicide is formed on a surface of the diffusion layer.

6. The semiconductor device according to claim 2 , further comprising a plurality of pads, wherein

the inductor is disposed in a spiral pattern along a periphery of the substrate above the substrate, and

the plurality of pads are disposed inside the inductor above the substrate.

7. The semiconductor device according to claim 2 , further comprising a plurality of pads, wherein

the inductor is disposed in a spiral pattern along a periphery of the substrate above the substrate, and

the plurality of pads are disposed outside the inductor above the substrate.

8. An electrical energy measurement instrument comprising:

a semiconductor device according to claim 2 , the semiconductor device comprising the inductor configured to detect a change in strength of a magnetic field, the change in strength of a magnetic field occurring according to a current flowing through a power line;

an amplification circuit configured to amplify a detection result of the inductor;

an AD converter configured to convert an amplification result of the amplification circuit into a digital signal; and

an arithmetic processing unit configured to calculate electrical energy consumed by the current flowing through the power line based on the digital signal.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 30, 2019
From: UCHIDA, SHINICHI; TANAKA, KEIICHIRO; KURAMOTO, TAKAFUMI
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 051388/0384 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 6, 2017
From: UCHIDA, SHINICHI; TANAKA, KEIICHIRO; KURAMOTO, TAKAFUMI
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 041888/0484 →
Priority Claims (1)
JP 2016-107283 · May 30, 2016 · national
Continuity (1)
Related Publication 20170345755A1 · Nov 30, 2017