Phase accumulation digital-to-analog converter (DAC)
A phase accumulation digital-to-analog converter (DAC) is provided. A digital-to-time converter (DTC), including a reference clock chain with N number of series connected delay elements, accepts a clock signal with a leading clock edge and supplies a set signal representing a first delay of the leading clock edge. A data clock chain including N number of series connected accumulators, accepts the clock signal with the leading clock edge, accepts a binary coded digital word, and supplies a reset signal representing a second delay of the leading clock edge, responsive to the digital word. A phase-to-time logic (PTL) receives the set and reset signals and supplies a DTC output signal representing the difference in delay between the set and reset signals. A time-to-voltage converter (TVC) charges a load capacitor every clock period in response to the DTC output signal to supply an analog output signal.
1. A phase accumulation digital-to-analog converter (DAC) comprising:
a digital-to-time converter (DTC) comprising:
a reference clock chain comprising N series connected delay elements, having an input to accept a clock signal with a leading clock edge and an output to supply a set signal representing a first delay of the leading clock edge, where the first delay duration is less than a clock signal period;
a data clock chain comprising N series connected accumulators, having an input to accept the clock signal with the leading clock edge, an input to accept a digital word bit value, and an output to supply a reset signal representing a second delay of the leading clock edge, responsive to the digital word, where the second delay is less than or equal to the clock signal period; and,
a phase-to-time logic (PTL) having inputs to receive the set and reset signals and an output to supply a DTC output signal representing a difference in delay between the set and reset signals.
2. The DAC of claim 1 wherein each accumulator comprises:
a delay element having an input to accept a corresponding leading clock edge and an output to supply a corresponding delayed leading clock edge;
a data capacitor having a first terminal connected to the output of the delay element and a second terminal, where each data capacitor has a weighted capacitance value responsive to the significance of a corresponding data bit in the digital word; and,
a data switch having a first terminal connected to the second terminal of the data capacitor and a second terminal connected to a first reference voltage, selectively closed in response to the corresponding digital word bit value.
3. The DAC of claim 2 wherein the DTC further comprises:
a data buffer comprising:
N data buffer chains, each data buffer chain having an input to accept a corresponding data bit from the digital word, and an output to selectively close the data switch in a corresponding accumulator in response to the digital word bit value, where each data buffer chain includes a number of series connected delay elements responsive to the significance of the data bit in the digital word.
4. The DAC of claim 1 wherein the PTL comprises:
an inverter having an input to accept the reset signal and an output to supply an inverted reset signal with a first delay;
a first delay element having an input to accept the reset signal and an output to supply a delayed reset signal with the first delay;
a second delay element having an input to accept the set signal and an output to supply a delayed set signal with the first delay;
a first p-type metal-oxide-semiconductor (PMOS) transistor having a first source/drain (S/D) connected to a second reference voltage having a higher potential than the first reference voltage, a gate to accept the inverted reset signal, and a second S/D;
a first n-type metal-oxide-semiconductor (NMOS) transistor having a first S/D connected to the second S/D of the first PMOS, a gate to accept the delayed set signal, and a second S/D;
a second NMOS transistor having a first S/D connected to the second S/D of the first NMOS, a gate to accept the inverted reset signal, and a second S/D connected to the first reference voltage;
a second PMOS transistor having a first S/D connected to the second reference voltage, a gate connected to the second S/D of the first NMOS, and a second S/D to provide the DTC output signal; and,
a third NMOS transistor having a first S/D connected to the second S/D of the second PMOS, a gate to accept the delayed reset signal, and a second S/D connected to the first reference voltage.
5. The DAC of claim 4 wherein the data clock chain further comprises:
an (N+1)th delay element having an input to accept the delayed leading clock edge from the Nth accumulator, and an output connected to the inverter input to supply the reset signal with a delay T PTL .
6. The DAC of claim 3 wherein the set signal has a duty cycle with a first portion of a period, initiated by a set signal leading clock edge, followed by a second portion of the period, initiated by a following clock edge opposite in polarity to the set signal leading clock edge, wherein the second portion is divided into an initial section and a trailing section;
the DAC further comprising:
a time-to-voltage converter (TVC) comprising:
a charger comprising:
a first switch having a first terminal and a second terminal, selectively closed in response to the DTC output signal;
a current source connected between the second reference voltage and the first terminal of the first switch;
a load capacitor having a first terminal connected to the second terminal of the first switch and a second terminal connected to the first reference voltage;
a buffer amplifier having a non-inverting input, an inverting input, and an output connected to the inverting input, supplying an analog output signal;
a second switch having a first terminal connected to the first terminal of the load capacitor and a second terminal connected to the non-inverting input of the buffer amplifier, selectively closed during the initial section of the set signal second portion; and,
a third switch having a first terminal connected to the first terminal of the load capacitor and a second terminal connected to the first reference voltage, selectively closed during the trailing section of the set signal second portion.
7. The DAC of claim 6 wherein each accumulator accepts the binary bit value of a corresponding digital word bit in the first portion of the clock period, and is refreshed in the second portion of the clock period.
8. The DAC of claim 7 wherein each accumulator accepts a binary bit value of a corresponding bit of a first digital word in a first clock period; and,
wherein each accumulator accepts a binary bit value of a corresponding bit of a second digital word, subsequent to the first digital word, in a second clock period, subsequent to the first clock period.
9. The DAC of claim 6 further comprises:
a plurality of M data clock chains, each data clock chain accepting N/M bit values of a digital word, and having an output to supply a corresponding reset signal, where N/M is a positive integer;
a plurality of M reference clock chains, each reference clock chain associated with a corresponding data clock chain;
a plurality of M PTLs, each PTL having an input to accept a reset signal from a corresponding data clock chain, an input to accept a set signal from a corresponding reference clock chain, and an output to supply a corresponding DTC output signal;
a plurality of M chargers, each charger having an input to accept a corresponding DTC output signal and an output connected to the load capacitor; and,
wherein the buffer amplifier supplies an analog output signal with a resolution of N bits.
10. The DAC of claim 6 wherein the reference clock chain comprises:
a positive reference clock chain to supply a positive set signal;
a negative reference clock chain to supply a negative set signal;
wherein the data clock chain comprises:
a positive data clock chain associated with the positive reference clock chain to supply a positive reset signal;
a negative data clock chain associated with the negative reference clock chain to supply a negative reset signal;
wherein each data buffer chain comprises:
a non-inverted output to selectively close a data switch in a corresponding positive data clock chain accumulator;
an inverted output to selectively close a data switch in a corresponding negative data clock chain accumulator;
wherein the PTL comprises:
a positive PTL to accept the positive set and reset signals, and supply a positive DTC output signal;
a negative PTL to accept the negative set and reset signals, and supply a negative DTC output signal;
wherein the TVC comprises:
a positive TVC to accept the positive DTC output signal and supply a positive analog quantity; and,
a negative TVC to accept the negative DTC output and supply a negative analog quantity.
11. A phase accumulation method for converting a digital word to an analog signal, the method comprising:
accepting a binary coded digital word and a clock signal initiated by a leading clock edge;
for each data bit in the digital word, creating a data delay referenced to the leading clock edge, responsive to the bit value and the significance of the data bit in the digital word;
sequentially summing the data delays from each accumulator for the digital word to create an accumulated delay duration in each clock signal period;
providing a constant value current to a load during the accumulated delay duration;
integrating a voltage on the load; and,
supplying an analog output signal responsive to the integrated voltage.
12. The method of claim 11 wherein accepting the digital word includes accepting a digital word with N number of data bits;
wherein sequentially summing the data delays from each accumulator to create accumulated delay duration includes:
adding a first delay to each of N sequential data delay summings to create a reset signal;
creating a set signal having a duration equal to N first delays;
finding the phase difference between the set and reset signals to create the accumulated delay duration.
13. A digital-to-time converter (DTC) comprising:
a reference clock chain comprising N series connected delay elements, having an input to accept a clock signal with a leading clock edge and an output to supply a set signal representing a first delay of the leading clock edge, where the first delay is less than a clock signal period;
a data clock chain comprising N series connected accumulators, having an input to accept the clock signal with the leading clock edge, an input to accept a digital word bit value, and an output to supply a reset signal representing a second delay of the leading clock edge, responsive to the digital word, where the second delay is less than or equal to the clock signal period; and,
a phase-to-time logic (PTL) having inputs to receive the set and reset signals and an output to supply a DTC output signal representing a difference in delay between the set and reset signals.
14. The DTC of claim 13 wherein each accumulator comprises:
a delay element having an input to accept a corresponding leading clock edge and an output to supply a corresponding delayed leading clock edge;
a data capacitor having a first terminal connected to the output of the delay element and a second terminal, where each data capacitor has a weighted capacitance value responsive to the significance of a corresponding data bit in the digital word; and,
a data switch having a first terminal connected to the second terminal of the data capacitor and a second terminal connected to a first reference voltage, selectively closed in response to the corresponding digital word bit value.
15. The DTC of claim 14 further comprising:
a data buffer comprising:
N data buffer chains, each data buffer chain having an input to accept a corresponding data bit from the digital word, and an output to selectively close the data switch in a corresponding accumulator in response to the digital word bit value, where each data buffer chain includes a number of series connected delay elements responsive to the significance of the data bit in the digital word.
16. A phase-to-time logic (PTL) comprising:
a first p-type metal-oxide-semiconductor (PMOS) transistor having a first source/drain (S/D) connected to a second reference voltage having a higher potential than the first reference voltage, a gate to accept the inverted reset signal, and a second S/D;
a first n-type metal-oxide-semiconductor (NMOS) transistor having a first S/D connected to the second S/D of the first PMOS, a gate to accept a delayed set signal, and a second S/D;
a second NMOS transistor having a first S/D connected to the second S/D of the first NMOS, a gate to accept the inverted reset signal, and a second S/D connected to the first reference voltage;
a second PMOS transistor having a first S/D connected to the second reference voltage, a gate connected to the second S/D of the first NMOS, and a second S/D to provide the DTC output signal; and,
a third NMOS transistor having a first S/D connected to the second S/D of the second PMOS, a gate to accept a delayed reset signal, and a second S/D connected to the first reference voltage.