Reverse direction high-electron-mobility logic gate

1. A logic NAND gate comprising:

a first input;

a second input;

an output;

a first reference voltage;

a second reference voltage, the second reference voltage having a higher voltage value that the first voltage reference;

a third reference, the third reference voltage having a lower voltage value that the first voltage reference;

a reverse direction high-electron-mobility transistor, the reverse direction high-electron-mobility transistor including:

a source connected to the first reference voltage,

a gate connected to the output, and

a drain connected to the output; and

logic implementing circuitry connected between the output and the third reference voltage, the logic implementing circuitry including:

a first transistor and a second transistor connected in series;

wherein a gate of the first transistor is connected to the first input; and,

wherein a gate of the second transistor is connected to the second input.

2. A logic NAND gate as in claim 1 , additionally comprising:

a third input;

wherein the logic implementing circuitry additionally includes a third transistor connected in series with the first transistor and the second transistor, wherein a gate of the third transistor is connected to the third input.

3. A logic NAND gate as in claim 2 :

wherein the third transistor is a high-electron-mobility transistor having a source connected to the third reference voltage and having a drain;

wherein the second transistor is a high-electron-mobility transistor having a source connected to the drain of the third transistor and having a drain; and

wherein the first transistor is a high-electron-mobility transistor having a source connected to the drain of the second transistor and having a drain connected to the output pin.

4. A logic NAND gate as in claim 3 , additionally comprising:

a resistance connected between the first reference voltage and the second reference voltage.

5. A logic NAND gate as in claim 1 :

wherein the second transistor is a high-electron-mobility transistor having a source connected to the third reference voltage and having a drain; and

wherein the first transistor is a high-electron-mobility transistor having a source connected to the drain of the second transistor and having a drain connected to the output pin.

6. A logic NAND gate as in claim 1 , additionally comprising:

a resistance connected between the first reference voltage and the second reference voltage.

7. A logic gate comprising:

a first input;

a second input;

an output;

a first reference voltage;

a second reference voltage, the second reference voltage having a higher voltage value that the first voltage reference;

a third reference, the third reference voltage having a lower voltage value that the first voltage reference;

at least one reverse direction high-electron-mobility transistor, the reverse direction high-electron-mobility transistor including:

at least one source connected to the first reference voltage,

at least one gate connected to the output, and

at least one drain connected to the output; and

logic implementing circuitry connected between the output and the third reference voltage, the logic implementing circuitry including:

a first transistor that includes a gate connected to the first input, and

a second transistor that includes a gate connected to the second input.

8. A logic gate as in claim 7 :

wherein the at least one reverse direction high-electron-mobility transistor includes:

a first high-electron-mobility transistor having a gate connected to the output pin, a source connected to the first reference voltage and a drain, and

a second high-electron-mobility transistor having a gate connected to the output pin, a source connected to the drain of the first high-electron-mobility transistor and a drain connected to the output pin.

9. A logic gate as in claim 8 :

wherein the first transistor is a high-electron-mobility transistor with a drain connected to the output and a source connected to the third reference voltage; and

wherein the second transistor is a high-electron-mobility transistor with a drain connected to the output and a source connected to the third reference voltage.

10. A logic gate as in claim 9 , additionally comprising:

a resistance connected between the first reference voltage and the second reference voltage.

11. A logic gate as in claim 7 :

wherein the first transistor is a high-electron-mobility transistor with a drain connected to the output and a source connected to the third reference voltage; and

wherein the second transistor is a high-electron-mobility transistor with a drain connected to the output and a source connected to the third reference voltage.

12. A logic gate as in claim 7 :

wherein the first transistor is a high-electron-mobility transistor with a drain connected to the output and a source; and

wherein the second transistor is a high-electron-mobility transistor with a drain connected to the source of the first transistor and a source connected to the third reference voltage.

13. A logic gate as in claim 7 :

wherein the logic implementing circuitry additionally includes a third transistor that includes a gate connected to a third input of the logic gate;

wherein the first transistor is a high-electron-mobility transistor with a drain connected to the output and a source;

wherein the second transistor is a high-electron-mobility transistor with a drain connected to the source of the first transistor and a source; and

wherein the third transistor is a high-electron-mobility transistor with a drain connected to the source of the second transistor and a source connected to the third reference voltage.

14. A logic gate as in claim 7 , additionally comprising:

a resistance connected between the first reference voltage and the second reference voltage.

15. A logic transmission gate comprising:

a first input/output;

a second input/output;

a control input;

a first reference voltage;

a second reference voltage, the second reference voltage having a lower voltage value that the first voltage reference;

a first reverse direction high-electron-mobility transistor, including:

a source connected to the first input/output,

a drain connected to the second input/output, and

a gate;

a second reverse direction high-electron-mobility transistor, including:

a drain connected to the first input/output,

a source connected to the second input/output, and

a gate connected to the gate of the first reverse direction high-electron-mobility transistor;

a transistor, including:

a gate connected to the control input,

a drain connected to the gate of the first reverse direction high-electron-mobility transistor, and

a source connected to the second reference voltage; and

a resistance connected between the gate of the first reverse direction high-electron-mobility transistor and the first reference voltage.

16. A logic transmission gate as sin claim 15 , wherein the resistance is a resistor or a depletion mode transistor.

17. A logic transmission gate as sin claim 15 , wherein the transistor is a high-electron-mobility transistor.