Timing insulation circuitry for partial reconfiguration of programmable integrated circuits
A device includes a platform implemented in programmable circuitry of the device. The platform is configured to communicate with a host data processing system. The device includes a first partial reconfiguration region implemented in the programmable circuitry and coupled to the platform. The first partial reconfiguration region is reserved for implementing user-specified circuitry. The device includes timing insulation circuitry implemented in the programmable circuitry and configured to isolate timing of signals passing between the platform and the first partial reconfiguration region.
1. A device, comprising:
a platform implemented in programmable circuitry of the device, wherein the platform includes a static platform circuitry having a bus endpoint and a platform partial reconfiguration region including a direct memory access (DMA) engine coupled to the bus endpoint, an interconnect coupled to the DMA engine, and a memory controller coupled to the DMA engine, wherein the platform partial reconfiguration region is configured to connect user-specified circuitry with the bus endpoint and an off-chip memory local to the device and distinct from a memory of a host data processing system;
a first partial reconfiguration region implemented in the programmable circuitry and coupled to the platform, wherein the first partial reconfiguration region is reserved for implementing the user-specified circuitry;
timing insulation circuitry implemented in the programmable circuitry and configured to isolate timing of signals passing between the platform partial reconfiguration region of the platform and the first partial reconfiguration region; and
wherein the bus endpoint is configured to maintain a communication link with the host data processing system while the first partial reconfiguration region or the platform partial reconfiguration region or both the first partial reconfiguration region and the platform partial reconfiguration region are reconfigured.
2. The device of claim 1 , wherein the timing insulation circuitry includes a flip-flop on each signal passing between the platform and the first partial reconfiguration region.
3. The device of claim 1 , wherein the timing insulation circuitry is part of the static platform circuitry.
4. The device of claim 3 , wherein the timing insulation circuitry is implemented between a boundary of the first partial reconfiguration region and a boundary of the platform partial reconfiguration region.
5. The device of claim 4 , wherein the static platform circuitry of the platform remains unchanged while the platform partial reconfiguration region is reconfigured.
6. The device of claim 4 , wherein the static platform circuitry remains unchanged while the first partial reconfiguration region is reconfigured.
7. The device of claim 1 , wherein the timing insulation circuitry is implemented within the platform partial reconfiguration region at a boundary of the platform partial reconfiguration region adjacent to a boundary of the first partial reconfiguration region and the platform partial reconfiguration region.
8. The device of claim 7 , wherein the timing insulation circuitry remains unchanged while the platform partial reconfiguration region is reconfigured.
9. The device of claim 1 , wherein placement and routing of the timing insulation circuitry is unchanged when circuitry of the platform is modified.
10. The device of claim 1 , wherein the timing insulation circuitry remains unchanged while a modified version of the platform is implemented in the device, wherein the modified version of the platform includes a modification of one or more of the signals that pass between the platform and the first partial reconfiguration region.
11. A method, comprising:
providing a platform implemented in programmable circuitry of a device, wherein the platform includes a static platform circuitry having a bus endpoint and a platform partial reconfiguration region including a direct memory access (DMA) engine coupled to the bus endpoint, an interconnect coupled to the DMA engine, and a memory controller coupled to the DMA engine, wherein the platform partial reconfiguration region is configured to connect user-specified circuitry with the bus endpoint and an off-chip memory local to the device and distinct from a memory of a host data processing system;
providing a first partial reconfiguration region implemented in the programmable circuitry and coupled to the platform, wherein the first partial reconfiguration region is reserved for implementing the user-specified circuitry;
providing timing insulation circuitry implemented in the programmable circuitry and configured to isolate timing of signals passing between the platform partial reconfiguration region of the platform and the first partial reconfiguration region; and
implementing a modified version of the platform circuitry in the device while keeping the timing insulation circuitry unchanged; and
wherein the bus endpoint is configured to maintain a communication link with the host data processing system while the first partial reconfiguration region or the platform partial reconfiguration region or both the first partial reconfiguration region and the platform partial reconfiguration region are reconfigured.
12. The method of claim 11 , wherein the timing insulation circuitry includes a flip-flop on each signal passing between the platform and the first partial reconfiguration region.
13. The method of claim 11 , wherein the modified version of the platform includes a modification of one or more of the signals that pass between the platform and the first partial reconfiguration region.
14. The method of claim 11 , wherein the timing insulation circuitry is part of the static platform circuitry.
15. The method of claim 14 , wherein the platform includes a platform partial reconfiguration region coupled to the first partial reconfiguration region, and wherein the timing insulation circuitry is implemented between a boundary of the first partial reconfiguration region and a boundary of the platform partial reconfiguration region.
16. The method of claim 15 , wherein the static platform circuitry of the platform remains unchanged while the platform partial reconfiguration region is reconfigured.
17. The method of claim 15 , wherein the static platform circuitry remains unchanged while the first partial reconfiguration region is reconfigured.
18. The method of claim 11 , wherein the timing insulation circuitry is implemented within the platform partial reconfiguration region at a boundary of the platform partial reconfiguration region adjacent to a boundary of the first partial reconfiguration region and the platform partial reconfiguration region.
19. The method of claim 18 , wherein the timing insulation circuitry remains unchanged while the platform partial reconfiguration region is reconfigured.
20. The method of claim 11 , wherein placement and routing of the timing insulation circuitry is unchanged when circuitry of the platform is modified.