Routerless networks-on-chip
The disclosed technology concerns methods, apparatus, and systems for designing and generating networks-on-chip (“NoCs”), as well as to hardware architectures for implementing such NoCs. The disclosed NoCs can be used, for instance, to interconnect cores of a chip multiprocessor (aka a “multi-core processor”). In one example implementation, a wire-based routerless NoC design is disclosed that uses deterministically specified wire loops to connect the cores of the chip multiprocessor. The disclosed technology also comprises network interface architectures for use in an NoC. For example, a core can be equipped with a low-area-cost interface that is deadlock-free, uses buffering sharing, and provides low latency.
1. A computer-implemented method, comprising:
by a processor implementing an electronic design automation (EDA) design tool, generating a hardware description of a network-on-chip configured to interconnect a plurality of processing cores of a multi-core processor via routerless wiring paths, wherein the generating comprises:
inputting parameters describing a size of a topological mesh of nodes, the nodes of the mesh corresponding to processing cores of the multi-core processor;
generating a wiring layout for the network-on-chip by applying a path generation procedure that generates circular wiring paths connecting processing cores of a first layer of the topological mesh and recursively applying the path generation procedure to generate circular wiring paths connecting processing cores for one or more additional layers of the topological mesh; and
outputting the wiring layout.
2. The method of claim 1 , wherein the one or more additional layers of the topological mesh are concentric and interior to the first layer.
3. The method of claim 1 , wherein the path generation procedure generates the circular wiring paths such that every pair of nodes of the topologic mesh share at least one circular wiring path.
4. The method of claim 1 , wherein the path generation procedure generates the circular wiring paths for a respective layer of the topological mesh in a deterministic fashion that minimizes hop count among the circular wiring paths.
5. The method of claim 1 , wherein the hardware description is a hardware-design-language representation or a gate-level netlist.
6. One or more memory or storage devices storing computer-executable instructions which when executed cause the computer to perform the method of claim 1 .
7. A system, comprising:
a memory or storage device; and
one or more processors, the one or more processors being configured to implement an electronic design automation (EDA) tool for generating an integrated circuit design comprising multiple processing cores;
generating design data specifying wiring paths of a routerless network-on-chip configured to interconnect the multiple processing cores with one another; and
generating design data for network interfaces of the network-on-chip, the network interfaces facilitating injection of a network packet into the network-on-chip from a source processing core and ejection of the network packet from the network-on-chip at a destination core.
8. The system of claim 7 , wherein one or more of the network interfaces comprise extension buffers that are shared among multiple input ports of the one or more network interfaces.
9. The system of claim 7 , wherein the wiring paths comprise a set of unidirectional wiring loops arranged so that every pair of processing cores shares at least one of the unidirectional wiring loops.
10. The system of claim 7 , wherein the generating comprises applying a deterministic wring path selection procedure.
11. The system of claim 7 , wherein the wiring paths all have a rectangular shape.