Packages and packaging methods for semiconductor devices, and packaged semiconductor devices
Packages and packaging methods for semiconductor devices, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes a molding compound and a plurality of through-vias disposed in the molding compound. The package includes an interconnect structure disposed over the plurality of through-vias and the molding compound. The interconnect structure includes a metallization layer. The metallization layer includes a plurality of contact pads and a fuse.
1. A method of packaging a semiconductor device, the method comprising:
disposing a molding compound around a plurality of integrated circuit dies;
forming a plurality of through-vias in the molding compound;
forming a first interconnect structure over a first side of the plurality of through-vias and the molding compound, the first interconnect structure comprising a metallization layer, the metallization layer comprising a plurality of conductive lines, a plurality of contact pads, and a plurality of fuses wherein the plurality of fuses lie within respective projections of outer peripheries of respective ones of the plurality of integrated circuit dies; and
forming a second interconnect structure over a second side of the plurality of through-vias and the molding compound, the second side being opposite the first side.
2. The method according to claim 1 , wherein forming the first interconnect structure comprises forming a metallization layer wherein one of the plurality of fuses is coupled to one of the plurality of integrated circuit dies by one of the plurality of through-vias and the second interconnect structure.
3. The method according to claim 2 , wherein a characterization of the one of the plurality of integrated circuit dies is programmable using the one of the plurality of fuses.
4. The method according to claim 3 , wherein the one of the plurality of fuses is programmable by blowing the one of the plurality of fuses using a laser.
5. The method according to claim 1 , further comprising coupling a plurality of conductors to portions of the second interconnect structure, and coupling the plurality of conductors to a substrate.
6. The method according to claim 1 , wherein disposing the molding compound, forming the plurality of through-vias, forming the first interconnect structure, and forming the second interconnect structure comprise forming a first packaged semiconductor device, and wherein the method further comprises:
coupling a conductor to each of the plurality of contact pads of the first interconnect structure; and
coupling the conductors to a second packaged semiconductor device.
7. A method of packaging a semiconductor device, the method comprising:
encapsulating in a molding compound an integrated circuit die having bond pads formed on a first side of the integrated circuit die;
forming a plurality of through-vias extending through the molding compound; and
forming over the molding compound and a second side of the integrated circuit die a metallization layer, the metallization layer including a plurality of contact pads and a fuse, the fuse being disposed outside of a footprint of the integrated circuit die in a top down view.
8. The method according to claim 7 , wherein encapsulating in a molding compound including forming the molding compound using a laminating process.
9. The method according to claim 7 , further comprising curing the molding compound using a heating process, infrared (IR) energy exposure process, or an ultraviolet (UV) light exposure process.
10. The method according to claim 7 , wherein forming a plurality of through-vias includes etching or drilling through the molding compound to form an aperture therein and then filling the aperture with a conductive material.
11. The method according to claim 7 , wherein forming a plurality of through-vias extending through the molding compound includes forming conductive material first and encapsulating the conductive material with the molding compound.
12. The method according to claim 7 , further comprising programming the integrated circuit die by blowing the fuse.
13. The method according to claim 12 , wherein the fuse is blown by laser ablation.
14. The method according to claim 7 , wherein the metallization layer includes a plurality of stacked metallization layers and further comprising forming the fuse in a topmost metallization layer the plurality of stacked metallization layers.
15. A method of packaging a semiconductor device, the method comprising:
encapsulating a die in a molding compound;
forming a through-via extending from a first side of the molding compound to a second side of the molding compound, the first side being opposite the second side; and
depositing over the first side of the molding compound and the through-via, a plurality of conductive lines, a plurality of conductive vias, a plurality of contact pads, and a plurality of fuses, the plurality of fuses being disposed in a fuse region, wherein at least one fuse of the plurality of fuses has a terminal that directly overlies and is vertically aligned with a respective on of the plurality of conductive vias and the respective on of the plurality of conductive vias directly overlies and is vertically aligned with the through-via, wherein the fuse region is offset from the die in a top down view.
16. The method according to claim 15 , wherein the plurality of conductive lines and the plurality of fuses are formed simultaneously in a same metallization layer.
17. The method according to claim 15 , further comprising programming the die by blowing one or more of the fuses.
18. The method of claim 17 , further comprising blowing one or more of the fuses using laser ablation.
19. The method of claim 17 , further comprising wire bonding a package device to the plurality of conductive lines.
20. The method of claim 17 , further comprising encapsulating a plurality of die in the molding compound.