Back-biasing regulation system and method for integrated circuits

1. A voltage regulation system for an integrated circuit, comprising:

a first regulator having a reference voltage as an input and having a first voltage output coupled as a back-bias voltage to a first load region within the integrated circuit, the first voltage output being based upon the reference voltage and a first sampled voltage output;

a first sampler for the first regulator coupled to receive the first voltage output and to provide the first sampled voltage output as feedback for the first regulator;

a second regulator having the first sampled voltage output as an input and having a second voltage output coupled as a back-bias voltage to a second load region within the integrated circuit, the second voltage output tracking the first voltage output and being based upon the first sampled voltage output and a second sampled voltage output; and

a second sampler for the second regulator coupled to receive the second voltage output and to provide the second sampled voltage output as feedback for the second regulator.

2. The voltage regulation system of claim 1 , wherein the first sampler and the second sampler comprise capacitors and switches controlled by a clock signal to provide switched-capacitor operation.

3. The voltage regulation system of claim 2 , wherein the clock signal has a variable frequency based upon the first sampled voltage output to reduce power consumption.

4. The voltage regulation system of claim 3 , wherein the variable frequency is increased when the first sampled voltage output drops below the reference voltage and is decreased when the first sampled voltage output rises above the reference voltage.

5. The voltage regulation system of claim 1 , wherein the integrated circuit comprises a semiconductor substrate, wherein the first load region comprises a well of a first dopant type within the semiconductor substrate, and wherein the second load region comprises a well of a second dopant type within the semiconductor substrate.

6. The voltage regulation system of claim 1 , wherein the second regulator is coupled to receive the first sampled voltage output through a divider, the divider causing the second voltage output to track the first voltage output by a symmetry ratio.

7. The voltage regulation system of claim 6 , wherein the divider is programmable.

8. The voltage regulation system of claim 6 , wherein the divider comprises capacitors and switches controlled by a clock signal to provide switched-capacitor operation, and wherein the clock signal has a variable frequency based upon the first sampled voltage output to reduce power consumption.

9. The voltage regulation system of claim 1 , wherein the first regulator comprises a first comparator having the reference voltage and the first sampled voltage output as inputs and having a first output coupled to a first charge pump, and wherein the second regulator comprises a second comparator having the first sampled voltage output and the second sampled voltage output as inputs and having a second output coupled to a second charge pump.

10. An integrated circuit, comprising:

a first load region within a semiconductor substrate having a first dopant type;

a second load region within the semiconductor substrate having a second dopant type;

a voltage regulation system, comprising:

a first regulator having a reference voltage as an input and having a first voltage output coupled as a back-bias voltage to the first load region, the first voltage output being based upon the reference voltage and a first sampled voltage output;

a first sampler for the first regulator coupled to receive the first voltage output and to provide the first sampled voltage output as feedback for the first regulator;

a second regulator having the first sampled voltage output as an input and having a second voltage output coupled as a back-bias voltage to the second load region, the second voltage output tracking the first voltage output and being based upon the first sampled voltage output and a second sampled voltage output; and

a second sampler for the second regulator coupled to receive the second voltage output and to provide the second sampled voltage output as feedback for the second regulator.

11. The integrated circuit of claim 10 , wherein the first sampler and the second sampler comprise capacitors and switches controlled by a clock signal to provide switched-capacitor operation.

12. The integrated circuit of claim 11 , wherein the clock signal has a variable frequency based upon the first sampled voltage output to reduce power consumption.

13. The integrated circuit of claim 10 , wherein the second regulator comprises a divider coupled to receive the first voltage output, the divider causing the second voltage output to track the first voltage output by a symmetry ratio.

14. The integrated circuit of claim 13 , wherein the divider is programmable, wherein the divider comprises capacitors and switches controlled by a clock signal to provide switched-capacitor operation, and wherein the clock signal has a variable frequency based upon the first sampled voltage output to reduce power consumption.

15. A method, comprising

with a first regulator within an integrated circuit,

receiving a reference voltage as an input;

generating a first voltage output based upon the reference voltage and a first sampled voltage output;

applying the first voltage output as a back-bias voltage to a first load region within the integrated circuit; and

sampling the first voltage output to provide the first sampled voltage output as feedback for the first regulator; and

with a second regulator within the integrated circuit,

receiving the first sampled voltage output as an input;

generating a second voltage output that tracks the first voltage output and that is based upon the first sampled voltage output and a second sampled voltage output;

applying the second voltage output as a back-bias voltage to a second load region within the integrated circuit; and

sampling the second voltage output to provide the second sampled voltage output as feedback for the second regulator.

16. The method of claim 15 , wherein sampling comprises controlling switches coupled to capacitors with a clock signal to provide switched-capacitor operation.

17. The method of claim 16 , further comprising varying a frequency for the clock signal based upon the first sampled voltage output to reduce power consumption.

18. The method of claim 17 , wherein the varying comprises increasing the frequency when the first sampled voltage output drops below the reference voltage and decreasing the frequency when the first sampled voltage output rises above the reference voltage.

19. The method of claim 18 , wherein the adjusting comprises controlling switches coupled to capacitors with a clock signal to provide switched-capacitor operation, and further comprising varying a frequency for the clock signal based upon the first sampled voltage output to reduce power consumption.

20. The method of claim 15 , further comprising, with the second regulator, adjusting the first sampled voltage output by a symmetry ratio as part of the generating of the second voltage output.