Encoding and decoding information for detecting and correcting bit errors

1. An apparatus, comprising:

an encoder circuit block configured to receive input data, generate a plurality of parity bits from the input data; and order the input data and the plurality of parity bits to generate encoded data;

wherein the encoder circuit block is configured to generate each of the plurality of parity bits based upon selected bits of the input data and order the input data and the plurality of parity bits so that a decoder circuit block configured to decode the encoded data performs operations including detecting a no bit error, detecting and correcting a single bit error, detecting a double bit error, detecting and correcting an adjacent double bit error, and detecting an adjacent triple bit error;

wherein the encoder circuit block is configured to order the input data and the plurality of parity bits so that the encoded data begins with at least one of the plurality of parity bits; and

wherein the decoder is operable to detect the no bit error, detect and correct the single bit error, detect the double bit error, detect and correct the adjacent double bit error, and detect the adjacent triple bit error in a memory having a single memory bank used to store the encoded data and in a memory having a plurality of memory banks used to store the encoded data.

2. The apparatus of claim 1 , wherein the encoded data begins with two or more consecutive parity bits of the plurality of parity bits.

3. The apparatus of claim 1 , wherein the encoder circuit block is configured to generate the plurality of parity bits so that:

each syndrome corresponding to a single bit error is unique within a single bit error space; and

each syndrome corresponding to an adjacent double bit error is unique within an adjacent double bit error space.

4. The apparatus of claim 3 , wherein the encoder circuit block is configured to generate the plurality of parity bits so that at least one of the syndromes corresponding to the single bit error has a same value as at least one of the syndromes corresponding to the adjacent double bit error, wherein the syndromes corresponding to the single bit error have a different value of a P0 parity bit than the syndromes corresponding to the adjacent double bit error.

5. The apparatus of claim 4 , wherein the encoder circuit block is configured to generate the plurality of parity bits so that syndromes corresponding to the adjacent triple bit error are mutually exclusive with syndromes corresponding to the single bit error.

6. The apparatus of claim 5 , wherein the encoder circuit block is configured to generate the plurality of parity bits so that at least one of the syndromes corresponding to the adjacent double bit error overlaps with at least one of the syndromes corresponding to the adjacent triple bit error, wherein the syndromes corresponding to the adjacent double bit error have a different value of the P0 parity bit than the syndromes corresponding to the adjacent triple bit error.

7. The apparatus of claim 6 , wherein the encoder circuit block is configured to generate the plurality of parity bits so that at least two syndromes corresponding to the adjacent triple bit error have a same value.

8. The apparatus of claim 6 , wherein the encoder circuit block is configured to generate the plurality of parity bits so that the decoder circuit block configured to decode the encoded data performs operations including correcting the adjacent triple bit error, wherein each syndrome corresponding to the adjacent triple bit error is unique within an adjacent triple bit error space.

9. The apparatus of claim 1 , further comprising:

the decoder circuit block, wherein the decoder circuit block is configured to generate syndrome bits from the encoded data and, based upon the generated syndrome bits, detect the no bit error, detect and correct the single bit error, detect the double bit error, detect and correct the adjacent double bit error, and detect the adjacent triple bit error.

10. The apparatus of claim 9 , wherein the decoder circuit block is further configured to correct the adjacent triple bit error.

11. An apparatus, comprising:

a decoder circuit block configured to receive encoded data and generate a plurality of syndrome bits from the encoded data;

wherein the decoder circuit block is configured, in response to generating the plurality of syndrome bits, to perform operations including detecting a no bit error, detecting and correcting a single bit error, detecting a double bit error, detecting and correcting an adjacent double bit error, and detecting an adjacent triple bit error; and

wherein the encoded data includes input data and a plurality of parity bits and is ordered to begin with at least one of the plurality of parity bits; and

wherein the decoder is operable to detect the no bit error, detect and correct the single bit error, detect the double bit error, detect and correct the adjacent double bit error, and detect the adjacent triple bit error in a memory having a single memory bank used to store the encoded data and in a memory having a plurality of memory banks used to store the encoded data.

12. The apparatus of claim 11 , wherein the encoded data begins with two or more consecutive parity bits of the plurality of parity bit.

13. The apparatus of claim 11 , wherein the decoder circuit block is configured to generate the plurality of syndrome bits so that:

each syndrome corresponding to a single bit error is unique within a single bit error space; and

each syndrome corresponding to an adjacent double bit error is unique within an adjacent double bit error space.

14. The apparatus of claim 13 , wherein the decoder circuit block is configured to generate the plurality of syndrome bits so that:

at least one of the syndromes corresponding to the single bit error has a same value as at least one of the syndromes corresponding to the adjacent double bit error, wherein the syndromes corresponding to the single bit error have a different value of a P0 parity bit than the syndromes corresponding to the adjacent double bit error; and

each syndrome corresponding to the adjacent triple bit error has a value that is different than a value of each syndrome corresponding to the single bit error.

15. The apparatus of claim 14 , wherein the decoder circuit block is configured to generate the plurality of syndrome bits so that at least one of the syndromes corresponding to the adjacent double bit error overlaps with at least one of the syndromes corresponding to the adjacent triple bit error, wherein the syndromes corresponding to the adjacent double bit error have a different value of the P0 parity bit than the syndromes corresponding to the adjacent triple bit error.

16. The apparatus of claim 15 , wherein the decoder circuit block is configured to generate the plurality of syndrome bits so that at least two syndromes corresponding to the adjacent triple bit error have a same value.

17. The apparatus of claim 15 , wherein the decoder circuit block is further configured to correct the adjacent triple bit error, wherein each syndrome corresponding to the adjacent triple bit error is unique within an adjacent triple bit error space.

18. The apparatus of claim 11 , wherein the decoder circuit block is further configured to correct the adjacent triple bit error.

19. A method of encoding data for error correction, comprising:

receiving input data;

generating a plurality of parity bits for the input data based on selected bits of the input data;

arranging the input data into encoded data by ordering the input data and the plurality of parity bits so that a decoder circuit block configured to decode the encoded data performs operations including detecting a no bit error, detecting and correcting a single bit error, detecting a double bit error, detecting and correcting an adjacent double bit error, and detecting an adjacent triple bit error;

wherein the encoder data begins with at least one of the plurality of parity bits storing the encoded data in a memory;

wherein the operations are independent of a number of memory banks within the memory; and

wherein the decoder is operable to detect the no bit error, detect and correct the single bit error, detect the double bit error, detect and correct the adjacent double bit error, and detect the adjacent triple bit error in the memory when the memory has a single memory bank used to store the encoded data and when the memory has a plurality of memory banks used to store the encoded data.

20. The method of claim 19 , where the decoding further comprises correcting the adjacent triple bit errors.