Three-dimensional memory device having zigzag slit structures and method for forming the same

1. A three-dimensional (3D) memory device, comprising:

a substrate;

a memory stack comprising interleaved conductive layers and dielectric layers above the substrate;

an array of memory strings each extending vertically through the memory stack; and

a plurality of slit structures laterally dividing the array of memory strings into a plurality of memory regions, wherein each of the plurality of slit structures extends vertically through the memory stack and extends laterally in a first zigzag pattern in a plan view.

2. The 3D memory device of claim 1 , wherein the first zigzag pattern is symmetrical.

3. The 3D memory device of claim 1 , wherein the first zigzag pattern comprises a plurality of turns each at a same angle.

4. The 3D memory device of claim 3 , wherein the angle is 60°.

5. The 3D memory device of claim 1 , where an edge of the first zigzag pattern is wavelike.

6. The 3D memory device of claim 1 , wherein at least one of the slit structures comprises a plurality of contact hole structures joined laterally.

7. The 3D memory device of claim 1 , wherein:

at least one of the slit structures comprises a plurality of contact hole structures;

at least some of the contact hole structures are joined laterally; and

at least two of the contact hole structures are separated laterally.

8. The 3D memory device of claim 6 , wherein one or more of the contact hole structures at turns of the first zigzag pattern have a nominally circular shape in the plan view.

9. The 3D memory device of claim 8 , wherein the rest of the contact hole structures not at the turns of the first zigzag pattern have a nominally oval shape in the plan view.

10. The 3D memory device of claim 9 , wherein a critical dimension of each of the contact hole structures at turns of the first zigzag pattern is larger than a critical dimension of each of the rest of the contact hole structures not at the turns of the first zigzag pattern.

11. The 3D memory device of claim 8 , wherein a critical dimension of each of the contact hole structures at turns of the first zigzag pattern is larger than a critical dimension of each of the channel hole structures.

12. The 3D memory device of claim 1 , wherein the plurality of slit structures are spaced apart in a same pitch.

13. The 3D memory device of claim 1 , further comprising a plurality of top select gate (TSG) cuts, wherein each of the plurality of TSG cuts extends vertically through part of the memory stack and extends laterally in a second zigzag pattern nominally parallel to the first zigzag pattern in the plan view.

14. A method for forming a three-dimensional (3D) memory device, comprising:

forming a dielectric stack comprising interleaved sacrificial layers and dielectric layers above a substrate;

forming a plurality of channel holes and a plurality of contact holes through the dielectric stack, wherein the plurality of contact holes are formed in a zigzag pattern in a plan view;

forming a channel structure in each of the channel holes;

forming a memory stack comprising interleaved conductive layers and dielectric layers by replacing, through the contact holes, the sacrificial layers in the dielectric stack with the conductive layers;

forming a plurality of recesses abutting a sidewall of each of the contact holes, such that the contact holes are joined laterally to form a slit opening; and

forming a spacer along a sidewall of the slit opening to electrically separate the conductive layers of the memory stack.

15. The method of claim 14 , wherein the plurality of channel holes and the plurality of contact holes are formed simultaneously through the dielectric stack.

16. The method of claim 14 , further comprising forming a slit contact over the spacer in the slit opening, wherein the slit contact is electrically connected to the channel structures.

17. The method of claim 14 , wherein upper portions of the contact holes are joined laterally after forming the plurality of channel holes and the plurality of contact holes.

18. The method of claim 14 , further comprising:

forming a sealing layer in each of the contact holes prior to forming the channel structure; and

removing the sealing layer from each of the contact holes after forming the channel structure.

19. The method of claim 14 , wherein forming the plurality of recesses comprises etching parts of the conductive layers in the memory stack that abut the sidewall of the contact hole.

20. A method for forming a three-dimensional (3D) memory device, comprising:

alternatingly depositing interleaved sacrificial layers and dielectric layers above a substrate;

etching through the interleaved sacrificial layers and dielectric layers to form a plurality of channel holes and a plurality of contact holes in a zigzag pattern in a plan view, wherein upper portions of the contact holes are joined laterally;

depositing a sealing layer in each of the contact holes;

etching away the sealing layer in each of the contact holes after depositing a channel structure in each of the channel holes;

replacing, through the contact holes, the sacrificial layers with a plurality of conductive layers;

etching parts of the conductive layers abutting a sidewall of each of the contact holes, such that lower portions of the contact holes are joined laterally; and

depositing a spacer along the sidewall of each of the contact holes.

21. The 3D memory device of claim 1 , wherein the plurality of slit structures each comprise a spacer surrounding a slit contact.