E-fuse for use in semiconductor device
View Patent ↗An e-fuse for use in a semiconductor device includes first and second electrodes; a gate metal coupling the first and second electrodes with each other; a first oxide layer formed under the gate metal; and a gate oxide layer formed between a bottom end of the gate metal and a top end of the first oxide layer.
1. An e-fuse for use in a semiconductor device, comprising:
first and second electrodes;
a first gate metal extending from the first electrode by a first length;
a second gate metal extending from the second electrode by the first length and in contact with the first gate metal;
a first oxide layer formed under the first and second gate metals, wherein the first oxide layer is formed under a portion where the first and second gate metals are in contact with each other, and wherein the first oxide layer is formed at the same level as a semiconductor layer;
a gate oxide layer formed between a bottom end of the first and second gate metals and a top end of the first oxide layer;
the semiconductor layer formed under the first and second gate metals and on both sides of the first oxide layer;
a silicon nitride layer formed over the first and second gate metals and the first and second electrodes; and
a second oxide layer formed over the silicon nitride layer, the semiconductor layer, the first oxide layer and on both sides of the first and second gate metals.
2. The e-fuse for use in a semiconductor device according to claim 1 , wherein the gate oxide layer is formed under the first and second gate metals and is contact with the top end of the first oxide layer corresponding to a bottom of the first and second gate metals.
3. The e-fuse for use in a semiconductor device according to claim 1 , wherein the first gate metal is formed as an n-type metal which is used in an NMOS, and the second gate metal is formed as a p-type metal which is used in a PMOS.
4. An e-fuse for use in a semiconductor device, comprising:
a first gate metal extending from a first electrode by a first length;
a second gate metal extending from a second electrode by the first length and in contact with the first gate metal, wherein the first and second gate metals are formed of different metals;
a first oxide layer formed under the first and second gate metals, wherein the first oxide layer is formed under a portion where the first and second gate metals are in contact with each other, and wherein the first oxide layer is formed at the same level as a semiconductor layer; and
a gate oxide layer formed between bottom ends of the first and second gate metals and a top end of the first oxide layer;
the semiconductor layer formed under the first and second gate metals and on both sides of the first oxide layer;
a silicon nitride layer formed over the gate metal and the first and second electrodes; and
a second oxide layer formed over the silicon nitride layer, the semiconductor layer, the first oxide layer and on both sides of the gate metal.
5. The e-fuse for use in a semiconductor device according to claim 4 , wherein the first gate metal is formed as an n-type metal which is used in an NMOS, and the second gate metal is formed as a p-type metal which is used in a PMOS.
6. The e-fuse for use in a semiconductor device according to claim 4 , wherein the gate oxide layer is formed under the first and second gate metals and is brought into contact with the top end of the first oxide layer corresponding to bottoms of the first and second gate metals.
7. A semiconductor device comprising at least one e-fuse, the e-fuse comprising:
first and second electrodes;
a first gate metal extending from the first electrode by a first length;
a second gate metal extending from the second electrode by the first length and in contact with the first gate metal, wherein the first and second gate metals are formed of different metals;
a first oxide layer formed under the first and second gate metals, wherein the first oxide layer is formed under a portion where the first and second gate metals are in contact with each other, and wherein the first oxide layer is formed at the same level as a semiconductor layer; and
a gate oxide layer formed between a bottom end of the gate metal and a top end of the first oxide layer,
the semiconductor layer formed under the first and second gate metals and on both sides of the first oxide layer;
a silicon nitride layer formed over the gate metal and the first and second electrodes; and
a second oxide layer formed over the silicon nitride layer, the semiconductor layer, the first oxide layer and on both sides of the gate metal.