Resistance change type memory

1. A resistance change type memory comprising:

a semiconductor substrate having a first impurity concentration;

a first interconnect extending in a first direction perpendicular to a surface of the semiconductor substrate;

a second interconnect including a first semiconductor layer, the first semiconductor layer extending in a second direction parallel to the surface of the semiconductor substrate and having a second impurity concentration lower than the first impurity concentration;

a memory layer provided between the first interconnect and the first semiconductor layer;

a first transistor including a second semiconductor layer provided between the first interconnect and the semiconductor substrate, and a first gate facing the second semiconductor layer via a first gate insulating film in a third direction parallel to the surface of the semiconductor substrate; and

a third interconnect provided between the semiconductor substrate and the second semiconductor layer, and extending in the third direction.

2. The resistance change type memory according to claim 1 , wherein the second semiconductor layer has a third impurity concentration, and the third impurity concentration is higher than the second impurity concentration.

3. The resistance change type memory according to claim 1 , wherein the second interconnect includes a conductive layer extending in the third direction and coupled to the first semiconductor layer.

4. The resistance change type memory according to claim 3 , wherein the first semiconductor layer is a layer including silicon.

5. The resistance change type memory according to claim 4 , wherein the conductive layer is a compound layer including silicon.

6. The resistance change type memory according to claim 1 , wherein the second impurity concentration is lower than 1×10 18 cm −3 .

7. The resistance change type memory according to claim 1 , wherein the second semiconductor layer includes an n-type impurity.

8. A resistance change type memory comprising:

a semiconductor substrate having a first impurity concentration;

first and second layers extending in a first direction parallel to a surface of the semiconductor substrate, the first and second layers being aligned in a second direction crossing the first direction;

first, second, third and fourth semiconductor layers extending in the second direction, the first, second, third and fourth semiconductor layers being aligned in the first direction between the first and second layers, the first and third semiconductor layers being coupled to the first layer, the second and fourth semiconductor layers being coupled to the second layer, and the first, second, third, and fourth semiconductor layers having a second impurity concentration lower than the first impurity concentration;

a first interconnect extending in a third direction perpendicular to the surface of the semiconductor substrate, the first interconnect being provided between the first semiconductor layer and the second semiconductor layer;

a second interconnect extending in the third direction, the second interconnect being provided between the second semiconductor layer and the third semiconductor layer;

a third interconnect extending in the third direction, the third interconnect being provided between the third semiconductor layer and the fourth semiconductor layer;

a first memory layer provided between the first semiconductor layer and the first interconnect;

a second memory layer provided between the second semiconductor layer and the first interconnect;

a third memory layer provided between the second semiconductor layer and the second interconnect;

a fourth memory layer provided between the third semiconductor layer and the second interconnect;

a fifth memory layer provided between the third semiconductor layer and the third interconnect;

a sixth memory layer provided between the fourth semiconductor layer and the third interconnect;

a first transistor including a fifth semiconductor layer provided between the first interconnect and the semiconductor substrate, and a first gate facing the fifth semiconductor layer via a first gate insulating film in the first direction;

a second transistor including a sixth semiconductor layer provided between the second interconnect and the semiconductor substrate, and a second gate facing the sixth semiconductor layer via a second gate insulating film in the first direction;

a third transistor including a seventh semiconductor layer provided between the third interconnect and the semiconductor substrate, and a third gate facing the seventh semiconductor layer via a third gate insulating film in the first direction; and

a fourth interconnect provided between the semiconductor substrate and the fifth, sixth, and seventh semiconductor layers, and extending in the first direction.

9. The resistance change type memory according to claim 8 , further comprising:

a fifth interconnect extending in the third direction, the fifth interconnect being provided between the first semiconductor layer and the second semiconductor layer;

a seventh memory layer provided between the first semiconductor layer and the fifth interconnect;

an eighth memory layer provided between the second semiconductor layer and the fifth interconnect;

a fourth transistor including an eighth semiconductor layer provided between the fifth interconnect and the semiconductor substrate, and a fourth gate facing the eighth semiconductor layer via a fourth gate insulating film in the first direction; and

a sixth interconnect provided between the semiconductor substrate and the eighth semiconductor layer, and extending in the first direction,

wherein a dimension of the sixth interconnect in the second direction is larger than a dimension of the fourth interconnect in the second direction.

10. The resistance change type memory according to claim 9 , wherein

the fifth interconnect is provided between the first layer and the first interconnect with respect to the second direction.

11. The resistance change type memory according to claim 9 , wherein the first gate and the fourth gate are provided in a first conductive layer extending in the second direction.

12. The resistance change type memory according to claim 8 , wherein

the first gate is adjacent to the second gate in the first direction, and

an insulating layer is provided between the first gate and the second gate.

13. The resistance change type memory according to claim 8 , wherein

the first gate is adjacent to the second gate in the first direction, and

the first gate and the second gate are provided in a second conductive layer extending in the second direction.

14. The resistance change type memory according to claim 8 , wherein the first layer is a conductor.

15. The resistance change type memory according to claim 8 , wherein

the first semiconductor layer is a silicon layer, and

the first layer is a conductive silicon compound layer.

16. The resistance change type memory according to claim 8 , wherein a third impurity concentration of the fifth semiconductor layer is higher than the second impurity concentration.

17. The resistance change type memory according to claim 8 , wherein the second impurity concentration is lower than 1×10 18 cm −3 .

18. The resistance change type memory according to claim 8 , wherein the first semiconductor layer includes an n-type impurity.

19. The resistance change type memory according to claim 8 , wherein

the first layer, the first semiconductor layer, and the third semiconductor layer are provided in a word line, and

the word line has a comb-like planar shape.