Time-to-digital converter circuit
A time-to-digital converter circuit includes a logic gate coupled to receive a first trigger signal indicative of a first clock signal and a second trigger signal indicative of a second clock signal. The logic gate is to generate a logic gate output signal responsive to the earlier of the first or second trigger signals to be a logic high. A synchronization circuit is included and is coupled to the logic gate and is configured to synchronize the logic gate output signal to a third clock to produce a synchronization output signal. A counter circuit counts pulses of the synchronization output signal.
1. A time-to-digital converter circuit, comprising:
a first logic gate coupled to receive a first trigger signal indicative of a first clock signal and a second trigger signal indicative of a second clock signal, the first logic gate to generate a logic gate output signal responsive to the earliest of the first or second trigger signals to be a logic high;
a synchronization circuit coupled to the first logic gate and configured to synchronize the logic gate output signal to a third clock to produce a synchronization output signal;
a pulse counter circuit to count pulses of the synchronization output signal; and
a circuit to stop the pulse counter counting pulses that includes a first logic gate, a delay element, and a flip-flop.
2. The time-to-digital converter circuit of claim 1 , wherein the first logic gate includes an exclusive-OR gate.
3. The time-to-digital converter circuit of claim 1 , further comprising:
a first trigger circuit to receive the first clock and the third clock and to generate the first trigger signal, wherein the first trigger circuit is to assert the first trigger signal responsive to an asserted edge of the third clock coincident with the first clock asserted high; and
a second trigger circuit to receive the second clock and the third clock and to generate the second trigger signal, wherein the second trigger circuit is to assert the second trigger signal responsive to an asserted edge of the third clock coincident with the second clock asserted high.
4. The time-to-digital converter circuit of claim 3 , wherein:
the first trigger circuit comprises a plurality of serially-connected flip-flops; and
the second trigger circuit comprises a plurality of serially-connected flip-flops.