IP Library Granted Patent US 10,692,424
Granted Patent B2
US 10,692,424 · App. 15/862,618 · Granted Jun 23, 2020

Organic electroluminescent display panel, driving method thereof and display device

Inventors: Dongxu Xiang (Shanghai, CN); Yue Li (Shanghai, CN); Zeyuan Chen (Shanghai, CN); Xiangzi Kong (Shanghai, CN); Xingyao Zhou (Shanghai, CN); Chuanli Leng (Shanghai, CN); Yuan Li (Shanghai, CN)
Assignee: SHANGHAI TIANMA AM-OLED CO., LTD.
G09G3/3208G09G2310/0264G09G2320/0653
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Quick Facts
Patent No.
US 10,692,424
App. No.
15/862,618
Granted
Jun 23, 2020
Kind
B2
Abstract

The disclosure discloses an organic electroluminescent display panel, a driving method thereof and a display device, where the dimming mode is taken to drive and each frame of scanning time is divided into the display area scanning time and the front-back porch time. Where each line of pixel circuits located in the display area of the organic electroluminescent display panel are scanned during the display area scanning time; and the drive circuit is adjusted during the front-back porch time. Where the front-back porch time is less than the display area scanning time, and the front-back porch time is the common multiple of the respective clock signal cycles in the gate drive circuit of the organic electroluminescent display panel.

Claims (38)

1. A driving method of an organic electroluminescent display panel, comprising:

controlling a light emitting drive circuit to provide a light emitting control signal with a set light emitting cycle during each frame of scanning time;

dividing the each frame of scanning time into display area scanning time M and front-back porch time N; and

scanning each line of pixel circuits located in a display area of the organic electroluminescent display panel during the display area scanning time; wherein

the display area scanning time M and the front-back porch time N satisfy following conditions:

M>N and N=k*A; k is an integer greater than zero, A is a least common multiple of respective clock signal cycles in a gate drive circuit of the organic electroluminescent display panel, and the gate drive circuit comprises a scanning drive circuit and the light emitting drive circuit;

wherein k=b*M/((n-b)*A); wherein b is a positive integer and n is the number of the light emitting cycles;

wherein b/n≤0.2.

2. The driving method of the organic electroluminescent display panel of claim 1 , wherein 1≤k≤0.01M/A.

3. The driving method of the organic electroluminescent display panel of claim 1 , wherein 1≤k≤0.05a*M/A; wherein a is a duty ratio of an effective light emitting signal within the cycle of the light emitting control signal.

4. The driving method of the organic electroluminescent display panel of claim 3 , wherein a=0.5.

5. The driving method of the organic electroluminescent display panel of claim 1 , wherein k=M/((n-1)*A).

6. The driving method of the organic electroluminescent display panel of claim 5 , wherein n≥5.

7. The driving method of the organic electroluminescent display panel of claim 1 , wherein k=0.

8. The driving method of the organic electroluminescent display panel of claim 1 , wherein A=4H, and H is time during which the scanning drive circuit scans a line of pixels.

9. An organic electroluminescent display panel, comprising:

pixel circuits arranged in an array and located in a display area, and a gate drive circuit located in a non-display area; wherein the gate drive circuit comprises a scanning drive circuit and a light emitting drive circuit;

the light emitting drive circuit is configured to provide a light emitting control signal with a set light emitting cycle during each frame of scanning time; wherein the each frame of scanning time is divided into display area scanning time M and front-back porch time N;

the scanning drive circuit is configured to scan each line of the pixel circuits during the display area scanning time; and

the display area scanning time M and the front-back porch time N satisfy following conditions:

M>N and N=k*A; k is an integer greater than zero, and A is a least common multiple of respective clock signal cycles in the gate drive circuit;

wherein k=b*M/((n-b)*A); wherein b is a positive integer and n is the number of the light emitting cycles;

wherein b/n≤0.2.

10. The organic electroluminescent display panel of claim 9 , wherein 1≤k≤0.01M/A.

11. The organic electroluminescent display panel of claim 9 , wherein 1≤k≤0.05a*M/A; wherein a is a duty ratio of an effective light emitting signal within the cycle of the light emitting control signal.

12. The organic electroluminescent display panel of claim 11 , wherein a=0.5.

13. The organic electroluminescent display panel of claim 9 , wherein k=M/((n-1)*A).

14. The organic electroluminescent display panel of claim 13 , wherein n≥5.

15. The organic electroluminescent display panel of claim 9 , wherein k=0.

16. The organic electroluminescent display panel of claim 9 , wherein A=4H, and H is time during which the scanning drive circuit scans a line of pixels.

17. A display device, comprising:

an organic electroluminescent display panel, wherein the organic electroluminescent display panel comprises: pixel circuits arranged in an array and located in a display area, and a gate drive circuit located in a non-display area; wherein the gate drive circuit comprises a scanning drive circuit and a light emitting drive circuit;

the light emitting drive circuit is configured to provide a light emitting control signal with a set light emitting cycle during each frame of scanning time; wherein the each frame of scanning time is divided into display area scanning time M and front-back porch time N;

the scanning drive circuit is configured to scan each line of the pixel circuits during the display area scanning time; and

the display area scanning time M and the front-back porch time N satisfy following conditions:

M>N and N=k*A; k is an integer greater than zero, and A is a least common multiple of respective clock signal cycles in the gate drive circuit;

wherein k=b*M/((n-b)*A); wherein b is a positive integer and n is the number of the light emitting cycles;

wherein b/n≤0.2.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 4, 2022
From: SHANGHAI TIANMA AM-OLED CO.,LTD.
To: WUHAN TIANMA MICRO-ELECTRONICS CO., LTD.; WUHAN TIANMA MICROELECTRONICS CO., LTD. SHANGHAI BRANCH
Reel/Frame 059498/0307 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 4, 2018
From: XIANG, DONGXU; LI, YUE; CHEN, ZEYUAN; KONG, XIANGZI; ZHOU, XINGYAO; LENG, CHUANLI; LI, YUAN
To: SHANGHAI TIANMA AM-OLED CO.,LTD.
Reel/Frame 044540/0836 →
Priority Claims (1)
CN 2017 1 0742194 · Aug 25, 2017 · national
Continuity (1)
Related Publication 20180130406A1 · May 10, 2018