Gate isolation plugs structure and method

1. A device comprising:

an elongated gate comprising a first length;

a first elongated dielectric spacer adjacent to a first sidewall of the elongated gate, and a second elongated dielectric spacer adjacent to a second sidewall of the elongated gate;

a gate isolation plug dividing the elongated gate into a first gate portion and a second gate portion, wherein the gate isolation plug comprises a second length greater than the first length, wherein the gate isolation plug only partially extends into the first and second elongated dielectric spacers;

a first Fin Field-Effect Transistor (FinFET) comprising a first semiconductor fin, wherein the first gate portion crosses over the first semiconductor fin; and

a second FinFET comprising a second semiconductor fin, wherein the second gate portion crosses over the second semiconductor fin.

2. The device of claim 1 , wherein a difference between the second length and the first length is at least three Angstroms.

3. The device of claim 1 , wherein a shape of the gate isolation plug comprises an oval shape.

4. The device of claim 1 , wherein a shape of the gate isolation plug comprises a square shape.

5. The device of claim 1 , wherein a shape of the gate isolation plug comprises a regular central portion and first and second irregular end portions.

6. A device comprising:

a first gate crossing over a first semiconductor fin;

a second gate crossing over a second semiconductor fin;

a first spacer layer in contact with a first sidewall of the first gate and a first sidewall of the second gate, the first spacer layer having a first portion, a second portion, and a third portion interposed between the first portion and the second portion, the first portion being in contact with the first sidewall of the first gate, the second portion being in contact with the first sidewall of the second gate, the third portion having a first concave sidewall;

a second spacer layer in contact with a second sidewall of the first gate and a second sidewall of the second gate, the second spacer layer having a fourth portion, a fifth portion, and a sixth portion interposed between the fourth portion and the fifth portion, the fourth portion being in contact with the second sidewall of the first gate, the fifth portion being in contact with the second sidewall of the second gate, the sixth portion having a second concave sidewall; and

a gate isolation plug between the first gate and the second gate, wherein the gate isolation plug extends from the first concave sidewall of the first spacer layer to the second concave sidewall of the second spacer layer.

7. The device of claim 6 , wherein a smallest width of the gate isolation plug interposed between the first gate and the second gate is greater than a largest width of the gate isolation plug interposed between the first portion and the second portion of the first spacer layer, wherein the smallest width and the largest width are measured in a direction parallel to a longitudinal axis of the first gate.

8. The device of claim 6 , wherein the first spacer layer and the second spacer layer are different sections of a single continuous layer.

9. The device of claim 6 , wherein a first length of the gate isolation plug is greater than a second length of the first gate, wherein the first length and the second length are measured in a direction parallel to a longitudinal axis of the first semiconductor fin.

10. The device of claim 9 , wherein a difference between the first length of the gate isolation plug and the second length of the first gate is at least three Angstroms.

11. The device of claim 6 , wherein the gate isolation plug comprises a thickness of about 5 to 200 Angstroms.

12. The device of claim 6 , wherein the first spacer layer comprises a first sidewall and a second sidewall, the first sidewall being opposite from the second sidewall, the first sidewall comprising the first concave sidewall, wherein the second sidewall is linear.

13. The device of claim 6 , wherein a smallest width of the gate isolation plug interposed between the first gate and the second gate is less than a largest width of the gate isolation plug interposed between the first portion and the second portion, wherein the smallest width and the largest width are measured in a direction parallel to a longitudinal axis of the first gate.

14. The device of claim 6 , wherein a first width of third portion is less than a second width of the first portion, wherein a third width of the sixth portion is less than a fourth width of the fourth portion, and wherein the first width, the second width, the third width, and the fourth width are measured in a direction parallel to the first semiconductor fin.

15. The device of claim 6 , wherein upper surfaces of the gate isolation plug, the first spacer layer, the second spacer layer, the first gate, and the second gate are level.

16. A device comprising:

first and second gates;

a first dielectric region in contact with a first sidewall of the first gate and a first sidewall of the second gate;

a second dielectric region in contact with a second sidewall of the first gate and a second sidewall of the second gate; and

a gate isolation plug between the first and second gates, wherein a first end portion of the gate isolation plug partially extends into the first dielectric region, and wherein a second end portion of the gate isolation plug partially extends into the second dielectric region.

17. The device of claim 16 , wherein a difference between a length of the gate isolation plug and a length of either of the first and second gates is at least three Angstroms.

18. The device of claim 16 , wherein the gate isolation plug comprises an oval shape.

19. The device of claim 16 , wherein the gate isolation plug comprises a square shape.

20. The device of claim 16 , wherein the gate isolation plug comprises a lemon shape.