Semiconductor pattern for monitoring overlay and critical dimension at post-etching stage and metrology method of the same
A semiconductor pattern for monitoring overlay and critical dimension at post-etching stage is provided in the present invention, which include a first inverted-T shaped pattern with a base portion and a middle portion extending from the base portion and a second pattern adjacent and spaced apart from the base portion of the first inverted-T shaped pattern, wherein the first inverted-T shaped pattern and the second pattern are composed of a plurality of spacer patterns spaced apart from each other.
1. A semiconductor pattern for monitoring an overlay and a critical dimension at a post-etching stage, comprising:
a first inverted-T shaped pattern with a base portion extending in a first direction and a middle portion extending from said base portion in a second direction orthogonal to said first direction; and
a second pattern adjacent and spaced apart from said base portion of said first inverted-T shaped pattern, wherein said first inverted-T shaped pattern is composed of a plurality of first spacer patterns spaced apart from each other and extending in said second direction, and said second pattern is composed of a plurality of second spacer patterns spaced apart from each other and extending in said second direction.
2. The semiconductor pattern for monitoring the overlay and the critical dimension at a post-etching stage of claim 1 , wherein said first inverted-T shaped pattern is symmetric with respect to said middle portion.
3. The semiconductor pattern for monitoring the overlay and the critical dimension at a post-etching stage of claim 1 , wherein said plurality of first spacer patterns are self-aligned double patterns, and said plurality of second spacer patterns are self-aligned double patterns.