Multi-modal data-driven clock recovery circuit
Multi-mode non-return-to-zero (NRZ) and orthogonal differential vector signaling (ODVS) clock and data recovery circuits having configurable sub-channel multi-input comparator (MIC) circuits for forming a composite phase-error signal from a plurality of data-driven phase-error signals generated using phase detectors in a plurality of receivers configured as ODVS sub-channel MICs generating orthogonal sub-channel outputs in a first mode and a separate first and second data driven phase-error signal from two receivers of a plurality of receivers configured as NRZ receivers in a second mode.
1. An apparatus comprising:
a plurality of multi-input comparators (MICs), each MIC configured to generate a respective MIC output by forming a linear combination of signals selected from wires of a multi-wire bus;
a first local oscillator configured to generate a first sampling clock and a second local oscillator configured to generate a second sampling clock;
a plurality of phase detectors, each phase detector configured to determine a data-driven phase error signal at each respective MIC output;
a mode controller for selecting between a first mode and a second mode:
wherein responsive to selection of the first mode, the mode controller is configured to:
configure the plurality of MICs by connecting inputs of each MIC to all the wires of the multi-wire bus according to a respective input permutation associated with a respective orthogonal sub-channel of a plurality of orthogonal sub-channels, the plurality of MICs generating a plurality of orthogonal sub-channel outputs;
configure the plurality of phase detectors to generate a composite phase-error signal to adjust the first local oscillator, the composite phase-error signal generated by forming a summation of the data-driven phase-error signals determined by the plurality of phase detectors, the data-driven phase-error signals associated with the plurality of orthogonal sub-channel outputs; and,
wherein responsive to selection of the second mode, the mode controller is configured to:
configure the plurality of MICs to generate first and second non-return-to-zero (NRZ) outputs by connecting inputs of a first MIC to a first pair of wires of the multi-wire bus and connecting a second MIC to a second pair of wires of the multi-wire bus;
configure the plurality of phase detectors generate a first local oscillator control signal to adjust the first local oscillator and to generate a second local oscillator control signal to adjust the second local oscillator.
2. The apparatus of claim 1 , wherein the mode controller is configured to disable at least one MIC of the plurality of MICs in the second mode.
3. The apparatus of claim 1 , wherein the first pair of wires of the multi-wire bus and the second pair of wires of the multi-wire bus correspond to adjacent pairs of wires.
4. The apparatus of claim 1 , wherein each MIC of the plurality of MICs comprises a corresponding sampling circuit configured to generate the respective MIC output.
5. The apparatus of claim 4 , further comprising a respective sub-channel specific delay element connected to the corresponding sampling circuit, the respective sub-channel specific delay element configured to receive the first sampling clock and to output a corresponding sub-channel specific sampling clock to the corresponding sampling circuit.
6. The apparatus of claim 1 , wherein the plurality of orthogonal sub-channel outputs are ensemble non-return-to-zero (ENRZ) sub-channel outputs.
7. The apparatus of claim 1 , wherein the mode controller is configured to connect the inputs of each MIC of the plurality of MICs to the wires of the multi-wire bus in the first mode according to a respective wire input permutation of a plurality of wire input permutations.
8. The apparatus of claim 7 , wherein each wire input permutation of the plurality of wire input permutations corresponds to a respective row of a plurality of rows of an orthogonal matrix.
9. The apparatus of claim 1 , wherein each data-driven phase error signal is generated based on a selection of a speculative decision feedback equalization (DFE) correction value of a pair of speculative DFE correction values.
10. The apparatus of claim 1 , further comprising a summation circuit configured to receive the plurality of data-driven phase-error signals and to responsively generate the composite phase-error signal.
11. A method comprising:
configuring at least one local oscillator of a plurality of local oscillators using a respective local oscillator control signal formed based on outputs of a plurality of multi-input comparators (MICs) connected to a plurality of wires of a multi-wire bus;
selectively configuring the plurality of MICs to (i) generate a plurality of orthogonal sub-channel outputs in a first mode by configuring at least one MIC to compare a set of at least three signals received via respective wires of the multi-wire bus, and (ii) to generate a set of non-return-to-zero (NRZ) outputs in a second mode by configuring a subset of the plurality of MICs to compare signals received on respective pairs of wires of the multi-wire bus;
generating, in the first mode, a plurality of data-driven phase-error signals based on the plurality of orthogonal sub-channel outputs and forming a composite phase-error signal by combining the plurality of data-driven phase-error signals, the composite phase-error signal provided to a local oscillator of the plurality of local oscillators; and
generating, in the second mode, a respective local oscillator control signal for each NRZ output of the set of NRZ outputs, and providing each respective local oscillator control signal to a respective local oscillator of the plurality of local oscillators.
12. The method of claim 11 , further comprising disabling a MIC of the plurality of MICs in the second mode.
13. The method of claim 11 , wherein the respective pairs of wires of the multi-wire bus comprise adjacent wires in the second mode.
14. The method of claim 11 , wherein the local oscillator provides a sampling clock to a plurality of samplers operating on the orthogonal sub-channel outputs in the first mode.
15. The method of claim 14 , further comprising applying a respective sub-channel specific delay to the sampling clock prior to providing the sampling clock to each sampler of the plurality of samplers.
16. The method of claim 11 , wherein the orthogonal sub-channel outputs are ensemble non-return-to-zero (ENRZ) sub-channel outputs.
17. The method of claim 11 , further comprising connecting the inputs of each MIC of the plurality of MICs to the wires of the multi-wire bus in the first mode according to a respective wire input permutation of a plurality of wire input permutations.
18. The method of claim 17 , wherein each wire input permutation of the plurality of wire input permutations corresponds to a respective row of a plurality of rows of an orthogonal matrix.
19. The method of claim 11 , wherein each data-driven phase-error signal is formed based on a selection of a speculative decision feedback equalization (DFE) correction value of a pair of speculative DFE correction values.
20. The method of claim 11 , wherein combining the plurality of data-driven phase-error signals comprises forming an analog summation of analog data-driven phase-error signals at a common node.