Hardware control method and hardware control system
A hardware control method and a hardware control system. The hardware control method is for an operating system to control at least one function circuit. The hardware control method includes: converting a first virtual address and a second virtual address from the operating system to a first intermediate address and a second intermediate address, respectively; converting the first intermediate address and the second intermediate address to a first extended physical address and a second extended physical address, respectively, wherein a starting position of the first extended physical address is distanced by a gap from a starting position of the second extended physical address; and converting the first extended physical address and the second extended physical address to a first hardware physical address and a second hardware physical address, respectively, wherein the first hardware physical address is adjacent to the second hardware physical address.
1. A hardware control method, for an operating system to control at least one function circuit, the hardware control method comprising:
converting a first virtual address and a second virtual address from the operating system to a first intermediate address and a second intermediate address, respectively;
converting the first intermediate address and the second intermediate address to a first extended physical address and a second extended physical address, respectively, wherein a starting position of the first extended physical address is spaced by a gap from a starting point of the second extended physical address;
converting the first extended physical address and the second extended physical address to a first hardware physical address and a second hardware physical address, respectively, wherein the first hardware physical address is adjacent to the second hardware physical address;
determining statuses of a first switch and a second switch corresponding to the first hardware physical address and the second hardware physical address, respectively; and
controlling the at least one function circuit according to the statuses of the first switch and the second switch.
2. The hardware control method according to claim 1 , wherein the first extended physical address corresponds to only one of the first switch, and the second extended physical switch corresponds to only one of the second switch.
3. The hardware control method according to claim 1 , wherein the first extended physical address and the second extended physical address have a common starting address, the hardware control method further comprising:
determining whether the first extended physical address is greater than an address of the starting address plus the gap; and
if the first extended physical address is not greater than the address of the starting address plus the gap, using the first extended physical address as the first hardware physical address in the converting the first extended physical address to the first hardware physical address.
4. The hardware control method according to claim 1 , wherein the converting the first intermediate physical address to the first extended physical address is performed by a converting circuit, and the gap is greater than or equal to a page size of the converting circuit.
5. The hardware control method according to claim 1 , wherein the gap is greater than or equal to 4 KB.
6. The hardware control method according to claim 1 , wherein the converting the first intermediate address to the first extended physical address is performed according to a look-up table.
7. The hardware control method according to claim 6 , wherein the virtual address is generated by the operating system through a virtual machine according to a command, and the look-up table is generated through the virtual machine.
8. The hardware control method according to claim 1 , wherein the converting the first intermediate address to the first extended physical address is performed according to an identifier of the operating system.
9. The hardware control method according to claim 1 , wherein the step of converting the first intermediate address to the first extended physical address is performed through a calculation equation.
10. A hardware control system, for an operating system to control at least one function circuit, the hardware control system comprising:
a first converting circuit, converting a first virtual address and a second virtual address from the operating system to a first intermediate address and a second intermediate address, respectively;
a second converting circuit, converting the first intermediate address and the second intermediate address to a first extended physical address and a second extended physical address, respectively, wherein a starting position of the first extended physical address is spaced by a gap from a starting point of the second extended physical address;
an analyzing circuit, converting the first extended physical address and the second extended physical address to a first hardware physical address and a second hardware physical address, respectively, wherein the first hardware physical address is adjacent to the second hardware physical address; and
the analyzing circuit further determining statuses of a first switch and a second switch corresponding to the first hardware physical address and the second hardware physical address, respectively, and controlling the at least one function circuit according to the statuses of the first switch and the second switch.
11. The hardware control system according to claim 10 , wherein the first extended physical address corresponds to only one of the first switch, and the second extended physical switch corresponds to only one of the second switch.
12. The hardware control system according to claim 10 , wherein the first extended physical address and the second extended physical address have a common starting address, and the analyzing circuit comprises:
a determining circuit, determining whether the first extended physical address is greater than an address of the starting address plus the gap; and if the first extended physical address is not greater than the address of the starting address plus the gap, the determining circuit using the first extended physical address as the first hardware physical address.
13. The hardware control system according to claim 10 , wherein the gap is greater than or equal to a page size of the second converting circuit.
14. The hardware control system according to claim 10 , wherein the gap is greater than or equal to 4 KB.
15. The hardware control system according to claim 10 , wherein the second converting circuit converts the first intermediate address to the first extended physical address according to a look-up table.
16. The hardware control system according to claim 15 , wherein the virtual address is generated by the operating system through a virtual machine according to a command, and the look-up table is generated through the virtual machine.
17. The hardware control system according to claim 10 , wherein the second converting circuit performs conversion according to an identifier corresponding to the operating system.
18. The hardware control system according to claim 10 , wherein the second converting circuit converts the first intermediate address to the first extended physical address through a calculation equation.