IP Library › Granted Patent US 10,705,996
Granted Patent B1
US 10,705,996 · App. 16/693,801 · Granted Jul 7, 2020

Handling operation collisions in a non-volatile memory

Inventors: Lyle E. Adams (San Jose, CA); Mark Ish (San Ramon, CA); Pushpa Seetamraju (San Jose, CA); Karl D. Schuh (Santa Cruz, CA); Dan Tupy (Roseville, CA)
Assignee: MICRON TECHNOLOGY, INC.
G06F13/376G06F3/061G06F3/067G06F3/0659G06F13/1631G06F13/1673
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Quick Facts
Patent No.
US 10,705,996
App. No.
16/693,801
Granted
Jul 7, 2020
Kind
B1
Abstract

A first operation identifier is assigned to a first operation directed to a memory component, the first operation identifier having an entry in a first data structure that associates the first operation identifier with a first plurality of buffer identifiers. It is determined whether the first operation collides with a prior operation assigned a second operation identifier, the second operation identifier having an entry in the first data structure that associates the second operation identifier with a second plurality of buffer identifiers. It is determined whether the first operation is a read or a write operation. In response to determining that the first operation collides with the prior operation and that the first operation is a read operation, the first plurality of buffer identifiers are updated with a buffer identifier included in the second plurality of buffer identifiers.

Claims (47)

1. A method comprising:

assigning a first operation identifier to a current operation directed to a memory component, the first operation identifier having a first entry in a first data structure that associates the first operation identifier with a first buffer identifier;

determining whether the current operation collides with a prior operation assigned a second operation identifier, the second operation identifier having a second entry in the first data structure that associates the second operation identifier with a second buffer identifier;

determining whether the current operation is a read or a write operation; and

updating, in response to determining that the current operation collides with the prior operation and that the current operation is a write operation, a latest flag to indicate that the second entry is no longer the latest of multiple operations directed to an address.

2. The method of claim 1 , wherein the determining whether the current operation collides with the prior operation comprises checking a second data structure for an entry that has an address that matches the address to which the current operation is directed.

3. The method of claim 1 , further comprising incrementing a counter associated with the first buffer identifier.

4. The method of claim 1 , wherein the first data structure is stored in a memory outside of the memory component.

5. The method of claim 1 , further comprising:

assigning a third operation identifier to a subsequent operation directed to a memory component, the third operation identifier having an entry in the first data structure that associates the third operation identifier with a plurality of buffer identifiers; and

updating, in response to determining that the subsequent operation collides with the current operation and that the subsequent operation is a read operation, the plurality of buffer identifiers to include a buffer identifier associated with the current operation.

6. The method of claim 5 , wherein the updating comprises replacing a buffer identifier included in the plurality of buffer identifiers with the buffer identifier associated with the current operation.

7. The method of claim 5 , further comprising:

determining that the prior operation is a read operation; and

updating, in response to determining that the subsequent operation collides with the prior operation and that the prior operation is a read operation, the entry in the first data structure associated with the second operation identifier to identify the third operation identifier.

8. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to:

assign a first operation identifier to a current operation directed to a memory component, the first operation identifier having a first entry in a first data structure that associates the first operation identifier with a first buffer identifier;

determine whether the current operation collides with a prior operation assigned a second operation identifier, the second operation identifier having a second entry in the first data structure that associates the second operation identifier with a second buffer identifier;

determine whether the current operation is a read or a write operation; and

update, in response to determining that the current operation collides with the prior operation and that the current operation is a write operation, a latest flag to indicate that the second entry is no longer the latest of multiple operations directed to an address.

9. The non-transitory computer-readable storage medium of claim 8 , wherein the determining whether the current operation collides with the prior operation comprises checking a second data structure for an entry that has an address that matches the address to which the current operation is directed.

10. The non-transitory computer-readable storage medium of claim 8 , wherein the processing device is further to increment a counter associated with the first buffer identifier.

11. The non-transitory computer-readable storage medium of claim 8 , wherein the first data structure is stored in a memory outside of the memory component.

12. The non-transitory computer-readable storage medium of claim 8 , wherein the processing device is further to:

assign a third operation identifier to a subsequent operation directed to a memory component, the third operation identifier having an entry in the first data structure that associates the third operation identifier with a plurality of buffer identifiers; and

update, in response to determining that the subsequent operation collides with the current operation and that the subsequent operation is a read operation, the plurality of buffer identifiers to include a buffer identifier associated with the current operation.

13. The non-transitory computer-readable storage medium of claim 12 , wherein the updating comprises replacing a buffer identifier included in the plurality of buffer identifiers with the buffer identifier associated with the current operation.

14. The non-transitory computer-readable storage medium of claim 12 , wherein the processing device is further to:

determine that the prior operation is a read operation; and

update, in response to determining that the subsequent operation collides with the prior operation and that the prior operation is a read operation, the entry in the first data structure associated with the second operation identifier to identify the third operation identifier.

15. A system comprising:

a memory component; and

a processing device, operatively coupled with the memory component, to:

assign a first operation identifier to a current operation directed to the memory component, the first operation identifier having a first entry in a first data structure that associates the first operation identifier with a first buffer identifier;

determine whether the current operation collides with a prior operation assigned a second operation identifier, the second operation identifier having a second entry in the first data structure that associates the second operation identifier with a second buffer identifier;

determine whether the current operation is a read or a write operation;

update, in response to determining that the current operation collides with the prior operation and that the current operation is a write operation, a latest flag to indicate that the second entry is no longer the latest of multiple operations directed to an address; and

increment a counter associated with the first buffer identifier.

16. The system of claim 15 , wherein the determining whether the current operation collides with the prior operation comprises checking a second data structure for an entry that has an address that matches the address to which the current operation is directed.

17. The system of claim 15 , wherein the first data structure is stored in a memory outside of the memory component.

18. The system of claim 15 , wherein the processing device is further to:

assign a third operation identifier to a subsequent operation directed to a memory component, the third operation identifier having an entry in the first data structure that associates the third operation identifier with a plurality of buffer identifiers; and

update, in response to determining that the subsequent operation collides with the current operation and that the subsequent operation is a read operation, the plurality of buffer identifiers to include a buffer identifier associated with the current operation.

19. The system of claim 18 , wherein the updating comprises replacing a buffer identifier included in the plurality of buffer identifiers with the buffer identifier associated with the current operation.

20. The system of claim 18 , wherein the processing device is further to:

determine that the prior operation is a read operation; and

update, in response to determining that the subsequent operation collides with the prior operation and that the prior operation is a read operation, the entry in the first data structure associated with the second operation identifier to identify the third operation identifier.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 25, 2019
From: ADAMS, LYLE E.; ISH, MARK; SEETAMRAJU, PUSHPA; SCHUH, KARL D.; TUPY, DAN
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051103/0335 →
Continuity (1)
Continuation 16223057 · Dec 17, 2018