Integrated magnetic inductors for embedded-multi-die interconnect bridge substrates
An embedded magnetic inductor coil is at least partially exposed in a recess that seats an embedded multi-chip interconnect bridge die on the coil. The embedded multi-chip interconnect bridge die provides a communications bridge between a dominant semiconductive device and a first semiconductive device.
1. A semiconductor device package, comprising:
an inductor coil in a semiconductor package substrate;
a magnetic material in interstices of the inductor coil;
a recess that projects a footprint onto at least a portion of the inductor coil; and
an embedded multi-die interconnect bridge (EMIB) die in the recess.
2. The semiconductor package substrate of claim 1 , further including wherein the magnetic material includes a surplus in the recess that insulates the inductor coil.
3. The semiconductor package substrate of claim 1 , further including an adhesive dielectric material in the recess that insulates the inductor coil.
4. The semiconductor device package of claim 1 , further including a recess fill material in the recess that contacts the recess and the EMIB die.
5. The semiconductor device package of claim 1 , further including wherein the magnetic material contacts the EMIB die with a surplus of the magnetic material, between the EMIB die and the inductor coil.
6. The semiconductor device package of claim 1 , further including wherein an adhesive dielectric contacts the inductor coil and the EMIB die at a backside of the EMIB die.
7. A semiconductor device package, comprising:
an inductor coil in a semiconductor package substrate;
a magnetic material in interstices of the inductor coil;
a recess that projects a footprint onto at least a portion of the inductor coil;
wherein the inductor coil is a first inductor coil;
a subsequent inductor coil in the semiconductor package substrate;
wherein the magnetic material is in interstices of the subsequent inductor coil;
wherein the recess projects the footprint onto at least a portion of the subsequent inductor coil; and
wherein the first inductor coil has a serpentine form factor, and wherein the subsequent inductor coil has a serpentine form factor.
8. The semiconductor device package of claim 7 :
wherein the first inductor coil has a serpentine form factor of a first orientation;
and
wherein the subsequent inductor coil has a serpentine form factor that is orthogonal to the subsequent inductor coil form factor.
9. The semiconductor device package of claim 7 :
wherein the first inductor coil has a serpentine form factor of a first orientation;
and
wherein the subsequent inductor coil has a spiral form factor.
10. A semiconductor device package, comprising:
an inductor coil in a semiconductor package substrate;
a magnetic material in interstices of the inductor coil;
a recess that projects a footprint onto at least a portion of the inductor coil; wherein the inductor coil is a spiral inductor coil.
11. A semiconductor device package, comprising:
an inductor coil in a semiconductor package substrate;
a magnetic material in interstices of the inductor coil;
a recess that projects a footprint onto at least a portion of the inductor coil;
an embedded multi-die interconnect bridge die in the recess;
a dominant die on a die side of the semiconductor package substrate and contacting the embedded multi-die interconnect bridge die;
a first die on the die side of the semiconductor package substrate and contacting the embedded multi-die interconnect bridge; and
a board on the semiconductor device substrate at a land side opposite the die side.
12. The semiconductor device package of claim 11 , further including
an external shell on the board, wherein the external shell is a dielectric material.
13. The semiconductor device package of claim 11 , further including
wherein the semiconductive device is part of a chipset.
14. The semiconductor device package of claim 11 , further including
wherein the semiconductive device is part of a chipset.
15. A semiconductor device package, comprising:
a semiconductor package substrate including a die side and a land side, with a first recess and a subsequent recess;
a first inductor coil in the semiconductor package substrate and the first recess, wherein the first recess projects a first footprint onto at least part of the first inductor coil;
a first magnetic material in interstices of the first inductor coil;
a first EMIB die in the first recess, above the first inductor coil;
a subsequent inductor coil in the semiconductor package substrate and the subsequent recess, wherein the subsequent recess projects a subsequent footprint onto at least part of the subsequent inductor coil;
a subsequent magnetic material in interstices of the subsequent inductor coil;
a subsequent EMIB die in the subsequent recess, above the subsequent inductor coil;
a dominant semiconductive device above the die side and in contact with the first EMIB die and the subsequent EMIB die;
a first semiconductive device above the die side and in contact with the first EMIB die; and
a subsequent semiconductive device above the die side and in contact with the subsequent EMIB die.
16. The semiconductor device package of claim 15 , further including:
a third recess in the semiconductor package substrate;
a third inductor coil in the semiconductor package substrate and the third recess, wherein the third recess projects a third footprint onto at least part of the third inductor coil;
a third magnetic material in interstices of the subsequent inductor coil;
a third EMIB die in the third recess, above the third inductor coil; and
wherein the dominant semiconductive device is in contact with the third EMIB die.
17. The semiconductor device package of claim 15 , further including:
a third recess in the semiconductor package substrate;
a third inductor coil in the semiconductor package substrate and the third recess, wherein the third recess projects a third footprint onto at least part of the third inductor coil;
a third magnetic material in interstices of the third inductor coil;
a third EMIB die in the third recess, above the third inductor coil;
a fourth recess in the semiconductor package substrate;
a fourth inductor coil in the semiconductor package substrate and the fourth recess, wherein the fourth recess projects a fourth footprint onto at least part of the fourth inductor coil;
a fourth magnetic material in interstices of the fourth inductor coil;
a fourth EMIB die in the fourth recess, above the fourth inductor coil;
wherein the dominant semiconductive device is in contact with the third and fourth EMIB dice;
a third second semiconductive device above the die side and in contact with the third EMIB die; and
a fourth semiconductive device above the die side and in contact with the fourth EMIB die.
18. The semiconductor device package of claim 15 , wherein the first inductor coil has a serpentine form factor, and wherein the subsequent inductor coil has a serpentine form factor.
19. The semiconductor device package of claim 15 , wherein the first inductor coil has a serpentine form factor, and wherein the subsequent inductor coil has a spiral form factor.
20. A process of forming a magnetic core inductor, comprising:
exposing at least part of an inductor coil in a recess in a semiconductor package substrate;
filling magnetic material into interstices in the inductor coil;
electrically insulating the inductor coil at exposed portions of the inductor coil;
seating a bridge die in the recess above the inductor coil and magnetic material;
connecting a dominant semiconductive device to the bridge die; and
connecting a first semiconductive device to the bridge die, to couple the dominant semiconductive device to the first semiconductive device through the bridge die.