IP Library › Granted Patent US 10,732,877
Granted Patent B1
US 10,732,877 · App. 16/364,054 · Granted Aug 4, 2020

Smart mapping table update post background operations

Inventors: Raghavendra Gopalakrishnan (Bengaluru, IN); Nicholas Thomas (Edinburgh, GB); Karin Inbar (Ramat-Hasharon, IL)
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
G06F3/064G06F3/0611G06F3/0679G06F12/0246G11C11/5621G06F2212/7201G06F2212/7203G11C2211/5641G11C2211/5643
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Quick Facts
Patent No.
US 10,732,877
App. No.
16/364,054
Granted
Aug 4, 2020
Kind
B1
Abstract

In one embodiment, there is a method for managing data in a storage device comprising a non-volatile memory having a plurality of jumbo blocks, each jumbo block having a separate and distinct physical block address. The method comprises performing a folding operation data associated with a first virtual address from a plurality of Single Level Cell (SLC) jumbo blocks of the non-volatile memory to one Multilevel Cell (MLC) jumbo block of the non-volatile memory, receiving a read request to read data associated with a first logical block address, identifying that the first virtual address is associated with the first logical block address, determining whether a jumbo block associated with the first logical block address meets pre-SLC-overwrite criteria. In response to a determination that the jumbo block associated with the first logical block address meets pre-SLC-overwrite criteria, reading data from the SLC jumbo block associated with the first virtual address. In response to a determination that the jumbo block associated with the first logical block address does not meet pre-SLC-overwrite criteria, reading data from the MLC jumbo block associated with the first virtual address.

Claims (73)

1. A method for managing data in a storage device comprising a non-volatile memory having a plurality of jumbo blocks, each jumbo block having a separate and distinct physical block address, the method comprising:

performing a folding operation on data associated with a first virtual address from a plurality of Single Level Cell (SLC) jumbo blocks of the non-volatile memory to one Multilevel Cell (MLC) jumbo block of the non-volatile memory;

receiving a read request to read data associated with a first logical block address;

identifying that the first virtual address is associated with the first logical block address;

determining whether a jumbo block associated with the first logical block address meets pre-SLC-overwrite criteria:

in response to a determination that the jumbo block associated with the first logical block address meets pre-SLC-overwrite criteria, reading data from the SLC jumbo block associated with the first virtual address;

in response to a determination that the jumbo block associated with the first logical block address does not meet pre-SLC-overwrite criteria, reading data from the MLC jumbo block associated with the first virtual address.

2. The method of claim 1 , wherein pre-SLC-overwrite criteria includes a criterion that is met when the SLC jumbo block corresponding to the logical block address has not been overwritten since the performing of the folding operation.

3. The method of claim 1 , further comprising:

maintaining a virtual-to-intermediate-physical mapping of the correspondence between the first virtual address and physical address of a corresponding SLC jumbo block;

maintaining an intermediate route mapping indicating whether there is an SLC jumbo block associated with the first virtual address with retrievable data;

wherein pre-SLC-overwrite criteria includes a criterion that is met when the intermediate route mapping indicates that there is an SLC jumbo block associated with the first virtual address with retrievable data; and

in response to a determination that the intermediate route mapping indicates that there is an SLC jumbo block associated with the first virtual address with retrievable data, and before reading data from the SLC jumbo block associated with the first virtual address:

identifying the physical address of the SLC jumbo block from the virtual-to-intermediate physical mapping.

4. The method of claim 3 , further comprising:

before receiving the read request, receiving a write request to write data to the non-volatile memory, and in response to receiving the write request:

writing data to the SLC jumbo block associated with the virtual block address and disassociating the SLC block with the virtual block address; and

updating the intermediate route mapping to indicate that data in the SLC jumbo block disassociated with the first virtual address is no longer retrievable such that the pre-SLC-overwrite criteria cannot be met.

5. The method of claim 1 , further comprising:

maintaining a logical-to-virtual mapping of the correspondence between the respective logical and virtual address for each jumbo block of data and maintaining a virtual-to-physical mapping of the correspondence between the respective virtual and physical address for each jumbo block of data.

6. The method of claim 5 , further comprising: in response to performing the folding operation, updating the virtual-to-physical mapping to associate the respective virtual address for the data with the physical address of the MLC jumbo block.

7. The method of claim 6 ,

in response to a determination that the jumbo block associated with the first logical block address does not meet pre-SLC-overwrite criteria, and before reading data from the MLC jumbo block associated with the first virtual address:

identifying the physical address of the MLC jumbo block from the virtual-to-physical mapping.

8. A memory controller for managing data in a storage device comprising a non-volatile memory having a plurality of jumbo blocks, each jumbo block having a separate and distinct physical block address, the memory controller configured to perform the operations of:

performing a folding operation on data associated with a first virtual address from a plurality of Single Level Cell (SLC) jumbo blocks of the non-volatile memory to one Multilevel Cell (MLC) jumbo block of the non-volatile memory;

receiving a read request to read data associated with a first logical block address;

identifying that the first virtual address is associated with the first logical block address;

determining whether a jumbo block associated with the first logical block address meets pre-SLC-overwrite criteria:

in response to a determination that the jumbo block associated with the first logical block address meets pre-SLC-overwrite criteria, reading data from the SLC jumbo block associated with the first virtual address;

in response to a determination that the jumbo block associated with the first logical block address does not meet pre-SLC-overwrite criteria, reading data from the MLC jumbo block associated with the first virtual address.

9. The memory controller of claim 8 , wherein pre-SLC-overwrite criteria includes a criterion that is met when the SLC jumbo block corresponding to the logical block address has not been overwritten since the performing of the folding operation.

10. The memory controller of claim 8 , wherein the memory controller is further configured to perform the operations of:

maintaining a virtual-to-intermediate-physical mapping of the correspondence between the first virtual address and physical address of a corresponding SLC jumbo block;

maintaining an intermediate route mapping indicating whether there is an SLC jumbo block associated with the first virtual address with retrievable data;

wherein pre-SLC-overwrite criteria includes a criterion that is met when the intermediate route mapping indicates that there is an SLC jumbo block associated with the first virtual address with retrievable data; and

in response to a determination that the intermediate route mapping indicates that there is an SLC jumbo block associated with the first virtual address with retrievable data, and before reading data from the SLC jumbo block associated with the first virtual address:

identifying the physical address of the SLC jumbo block from the virtual-to-intermediate physical mapping.

11. The memory controller of claim 10 , wherein the memory controller is further configured to perform the operations of:

before receiving the read request, receiving a write request to write data to the non-volatile memory, and in response to receiving the write request:

writing data to the SLC jumbo block associated with the virtual block address and disassociating the SLC block with the virtual block address; and

updating the intermediate route mapping to indicate that data in the SLC jumbo block disassociated with the first virtual address is no longer retrievable such that the pre-SLC-overwrite criteria cannot be met.

12. The memory controller of claim 8 , wherein the memory controller is further configured to perform the operations of:

maintaining a logical-to-virtual mapping of the correspondence between the respective logical and virtual address for each jumbo block of data and maintaining a virtual-to-physical mapping of the correspondence between the respective virtual and physical address for each jumbo block of data.

13. The memory controller of claim 12 , wherein the memory controller is further configured to perform the operation of:

in response to performing the folding operation, updating the virtual-to-physical mapping to associate the respective virtual address for the data with the physical address of the MLC jumbo block.

14. The memory controller of claim 13 , wherein the memory controller is further configured to perform the operation of:

in response to a determination that the jumbo block associated with the first logical block address does not meet pre-SLC-overwrite criteria, and before reading data from the MLC jumbo block associated with the first virtual address:

identifying the physical address of the MLC jumbo block from the virtual-to-physical mapping.

15. A data storage system for managing data in a storage device having a plurality of jumbo blocks, each jumbo block having a separate and distinct physical block address, the data storage system comprising:

a memory controller configured to perform the operations of:

performing a folding operation on data associated with a first virtual address from a plurality of Single Level Cell (SLC) jumbo blocks of the non-volatile memory to one Multilevel Cell (MLC) jumbo block of the non-volatile memory;

receiving a read request to read data associated with a first logical block address;

identifying that the first virtual address is associated with the first logical block address;

determining whether a jumbo block associated with the first logical block address meets pre-SLC-overwrite criteria:

in response to a determination that the jumbo block associated with the first logical block address meets pre-SLC-overwrite criteria, reading data from the SLC jumbo block associated with the first virtual address;

in response to a determination that the jumbo block associated with the first logical block address does not meet pre-SLC-overwrite criteria, reading data from the MLC jumbo block associated with the first virtual address.

16. The data storage system of claim 15 , wherein pre-SLC-overwrite criteria includes a criterion that is met when the SLC jumbo block corresponding to the logical block address has not been overwritten since the performing of the folding operation.

17. The data storage system of claim 15 , wherein the memory controller is further configured to perform the operations of:

maintaining a virtual-to-intermediate-physical mapping of the correspondence between the first virtual address and physical address of a corresponding SLC jumbo block;

maintaining an intermediate route mapping indicating whether there is an SLC jumbo block associated with the first virtual address with retrievable data;

wherein pre-SLC-overwrite criteria includes a criterion that is met when the intermediate route mapping indicates that there is an SLC jumbo block associated with the first virtual address with retrievable data; and

in response to a determination that the intermediate route mapping indicates that there is an SLC jumbo block associated with the first virtual address with retrievable data, and before reading data from the SLC jumbo block associated with the first virtual address:

identifying the physical address of the SLC jumbo block from the virtual-to-intermediate physical mapping.

18. The data storage system of claim 17 , wherein the memory controller is further configured to perform the operations of:

before receiving the read request, receiving a write request to write data to the non-volatile memory, and in response to receiving the write request:

writing data to the SLC jumbo block associated with the virtual block address and disassociating the SLC block with the virtual block address; and

updating the intermediate route mapping to indicate that data in the SLC jumbo block disassociated with the first virtual address is no longer retrievable such that the pre-SLC-overwrite criteria cannot be met.

19. The data storage system of claim 18 , wherein the memory controller is further configured to perform the operation of:

in response to performing the folding operation, updating the virtual-to-physical mapping to associate the respective virtual address for the data with the physical address of the MLC jumbo block.

20. The data storage system of claim 19 , wherein the memory controller is further configured to perform the operation of:

in response to a determination that the jumbo block associated with the first logical block address does not meet pre-SLC-overwrite criteria, and before reading data from the MLC jumbo block associated with the first virtual address:

identifying the physical address of the MLC jumbo block from the virtual-to-physical mapping.

Assignments (5)
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 4, 2019
From: GOPALAKRISHNAN, RAGHAVENDRA; THOMAS, NICHOLAS; INBAR, KARIN
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 048794/0100 →
Cited By (4)
US 12,260,101 US 12,360,914 US 12,366,995 US 12,650,766