IP Library Granted Patent US 10,734,483
Granted Patent B2
US 10,734,483 · App. 16/278,880 · Granted Aug 4, 2020

Semiconductor device

Inventors: Makoto Mizukami (Ibo Hyogo, JP); Masaru Furukawa (Himeji Hyogo, JP); Teruyuki Ohashi (Kawasaki Kanagawa, JP)
Assignees: Kabushiki Kaisha Toshiba; Toshiba Electronic Devices & Storage Corporation
H01L29/1608H01L29/045H01L29/0865H01L29/1095H01L29/517H01L29/66068H01L29/7804H01L29/7806
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Quick Facts
Patent No.
US 10,734,483
App. No.
16/278,880
Granted
Aug 4, 2020
Kind
B2
Abstract

A semiconductor device according to an embodiment includes a silicon carbide layer having first and second planes; a first silicon carbide region; second and third silicon carbide regions between the first silicon carbide region and the first plane; a fourth silicon carbide region between the second silicon carbide region and the first plane; a first and second gate electrodes; a suicide layer on the fourth silicon carbide region; a first electrode on the first plane having a first portion and a second portion, the first portion being in contact with the first silicon carbide region, the second portion being in contact with the suicide layer; a second electrode on the second plane; and an insulating layer between the first portion and the second portion having a first side surface and a second side surface, an angle of the first side surface being smaller than that of the second side surface.

Claims (23)

1. A semiconductor device comprising:

a silicon carbide layer having a first plane and a second plane opposite to the first plane;

a first silicon carbide region of a first conductivity type provided in the silicon carbide layer;

a second silicon carbide region of a second conductivity type provided between the first silicon carbide region and the first plane;

a third silicon carbide region of the second conductivity type provided between the first silicon carbide region and the first plane;

a fourth silicon carbide region of the first conductivity type provided between the second silicon carbide region and the first plane;

a first gate electrode provided on a side of the first plane of the silicon carbide layer;

a second gate electrode provided on a side of the first plane of the silicon carbide layer;

a first gate insulating layer provided between the first gate electrode and the second silicon carbide region;

a second gate insulating layer provided between the second gate electrode and the third silicon carbide region;

a silicide layer provided on the fourth silicon carbide region;

a first electrode provided on a side of the first plane of the silicon carbide layer, the first electrode having a first portion located between the first gate electrode and the second gate electrode and a second portion located between the first portion and the first gate electrode, the first portion being in contact with the first silicon carbide region between the second silicon carbide region and the third silicon carbide region, and the second portion being in contact with the silicide layer;

a second electrode provided on a side of the second plane of the silicon carbide layer; and

an insulating layer provided between the first portion and the second portion, having a first side surface on a side of the first portion and a second side surface on a side of the second portion, a first angle between the first side surface and the first plane being smaller than a second angle between the second side surface and the first plane.

2. The semiconductor device according to claim 1 , wherein the first portion is in contact with the second silicon carbide region.

3. The semiconductor device according to claim 1 , wherein the first angle is 70 degrees or less.

4. The semiconductor device according to claim 1 , wherein the insulating layer contains a silicon oxide.

5. The semiconductor device according to claim 1 , where n the first electrode has a first layer and a second layer, the first layer is located between the silicon carbide layer and the second layer, and the first layer contains titanium and the second layer contains aluminum.

6. The semiconductor device according to claim 1 , wherein junction between the first portion and the first silicon carbide region is Schottky junction.

7. The semiconductor device according to claim 1 , wherein the silicide layer is nickel silicide, titanium silicide, molybdenum silicide, or tungsten silicide.

8. The semiconductor device according to claim 1 , wherein the second angle is 80 degrees or more.

9. The semiconductor device according to claim 3 , wherein the second angle is 80 degrees or more.

10. The semiconductor device according to claim 1 , wherein the first conductivity type is n-type, and the second conductivity type is p-type.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 19, 2019
From: MIZUKAMI, MAKOTO; FURUKAWA, MASARU; OHASHI, TERUYUKI
To: KABUSHIKI KAISHA TOSHIBA; TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
Reel/Frame 048366/0749 →
Priority Claims (1)
JP 2018-173128 · Sep 14, 2018 · national
Continuity (1)
Related Publication 20200091296A1 · Mar 19, 2020
Cited By (2)
US 12,218,215 US 12,255,253