Dynamically configurable pipeline

1. A configurable multi-stage processing circuit, comprising:

an order-keeping circuit, and

a plurality of processing engines, each of the processing engines comprising:

an input port;

an output port; and

a circuit configured to perform a data processing function; and

a plurality of 2×2 switches,

wherein, for each of the processing engines,

the input port of the processing engine is electrically connected to an output port of only one of the 2×2 switches;

the output port of the processing engine is electrically connected to an input port of only another one of the 2×2 switches; and

the 2×2 switches are arranged such that the input port of the processing engine is electrically connectable to the output port of each of the processing engines by the 2×2 switches; and

wherein the 2×2 switches are configurable to:

connect the processing engines to form a first pipeline for processing a first data block based on routing information associated with the first data block; and

connect the processing engines to form a second pipeline for processing a second data block based on routing information associated with the second data block, the second pipeline being different from the first pipeline,

wherein each processing engine of the plurality of processing engines has a single input port and a single output port in the multi-stage processing circuit, and

wherein the order-keeping circuit is connected between an output port of one of the 2×2 switches and an input port of one of the processing engines, and

wherein the order-keeping circuit is configured to reorder processed data blocks based on identifications of the data blocks before the processed data blocks are sent to an output of the configurable multi-stage processing circuit.

2. The configurable multi-stage processing circuit of claim 1 , further comprising:

an order-keeping circuit configured to maintain an order of processing of a plurality of data blocks using the processing engines.

3. The configurable multi-stage processing circuit of claim 1 , wherein:

the processing engines comprises K processing engines, wherein K is equal to or greater than two;

the switches comprise K+1 2×2 switches; and

the output port of each of the K processing engines is connected to an input port of another processing engine of the K processing engines by one of the K+1 2×2 switches.

4. A circuit, comprising:

a plurality of processing engines, each of the processing engines including an input port and an output port;

an order-keeping circuit, and

a plurality of switches, each switch comprising two input ports and two output ports,

wherein, for each of the processing engines,

the input port of the processing engine is electrically connected to an output port of only one of the switches;

the output port of the processing engine is electrically connected to an input port of only another one of the switches;

the input port of the processing engine is electrically connected to the output port of each of the processing engines by the switches,

wherein each processing engine of the plurality of processing engines has a single input port and a single output port in the circuit,

wherein the order-keeping circuit is connected between an output port of one of the plurality of switches and an input port of one of the processing engines, and

wherein the order-keeping circuit is configured to reorder processed data blocks based on identifications of the data blocks before the processed data blocks are sent to an output of the circuit.

5. The circuit of claim 4 , wherein:

the switches are 2×2 switches.

6. The circuit of claim 4 , wherein:

the switches include a 2×2 switch and a N×M switch, wherein:

N and M are equal to or greater than 2;

an input port of the 2×2 switch is connected to an input of the circuit; and

an output port of the 2×2 switch is connected to an output of the circuit.

7. The circuit of claim 6 , wherein:

the N×M switch comprises a plurality of 2×2 switches.

8. The circuit of claim 4 , wherein:

the processing engines comprise K processing engines, wherein K is equal to or greater than two;

the switches comprise K+1 2×2 switches; and

the output port of each processing engine of the K processing engines is connected to an input port of another processing engine of the K processing engines by one of the switches.

9. The circuit of claim 8 , wherein each of the K+1 2×2 switches comprises:

two input ports; and

two output ports,

wherein, for each of K of the switches,

a first output port of the 2×2 switch is connected to a first input port of another 2×2 switch;

a second output port of the 2×2 switch is connected to the input port of a particular processing engine of the K processing engines; and

the output port of the particular processing engine is connected to a second input port of the another 2×2 switch.

10. The circuit of claim 4 , wherein:

each of the data blocks comprises a unique identification; and

the order-keeping circuit maintains an order of processing of the data blocks based on the unique identifications of the data blocks.

11. The circuit of claim 4 , wherein:

each of the data blocks comprises routing information associated with the data block; and

the switches are configurable to connect the processing engines to form a pipeline for the data block based on the routing information.

12. The circuit of claim 11 , wherein:

the order-keeping circuit maintains the order of processing of the data blocks based on the routing information associated with the data blocks.

13. The circuit of claim 4 , wherein:

the order-keeping circuit comprises a memory block configured to store a data block before or after the data block is processed by one of the processing engines.

14. A computer-implemented method, comprising:

receiving a data block to be processed by a processing circuit, wherein:

the processing circuit comprises a plurality of processing engines connected together by a plurality of switches, each switch comprising two input ports and two output ports; and

the data block comprises routing information;

configuring the switches based on the routing information to connect the processing engines to form a multi-stage pipeline; and

processing the data block using the multi-stage pipeline;

wherein the configuring comprises, for each of the plurality of processing engines:

electrically connecting an input port of the processing engine to an output of only one of the switches, and

electrically connecting an output port of the processing engine to an input of only another one of the switches, wherein each processing engine of the plurality of processing engines has a single input port and a single output port in the multi-stage pipeline, and

reordering, by an order-keeping circuit, processed data blocks based on identifications of the data blocks before the processed data blocks are sent to an output of the circuit, wherein the order-keeping circuit is connected between an output port of one of the plurality of switches and an input port of one of the processing engines.

15. The computer-implemented method of claim 14 , further comprising:

receiving a plurality of data blocks, each of the data blocks comprising an identification and corresponding routing information; and

determining an order of processing for the data block based on, the identification and the routing information of the data block and the corresponding identifications and routing information for the data blocks.

16. The computer-implemented method of claim 14 , further comprising:

receiving a plurality of data blocks, each of the data blocks comprising corresponding routing information and an identification;

for each of the data blocks,

configuring the switches based on the corresponding routing information to connect the processing engines to form a multi-stage pipeline; and

processing the data block using the multi-stage pipeline.