IP Library Granted Patent US 10,747,708
Granted Patent B2
US 10,747,708 · App. 15/915,185 · Granted Aug 18, 2020

Communication system between electronic devices

Inventors: Nevenka Kozomora (Windham, NH); Richard Vreeland (Litchfield, NH)
Assignee: Allegro MicroSystems, LLC
G06F13/4295G06F11/0745G06F11/0784H04J3/0602H04L12/4015G06F1/12H04J3/06H04L2012/40208
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Quick Facts
Patent No.
US 10,747,708
App. No.
15/915,185
Granted
Aug 18, 2020
Kind
B2
Abstract

A system for communicating between electronic devices on a communication bus includes a communication bus and one or more communication circuits each having an output driver coupled to the communication bus and each having an input terminal. Each communication circuit produces, in response to a request message, a data communication on the communication bus in a predetermined order with respect to data communications from other communication circuits so that the data communications from each communication circuit form a sequential data stream in response to the request message.

Claims (62)

1. A system comprising:

a communication bus;

a plurality of communication circuits each having an output driver coupled to the communication bus and each having an input terminal; and

a synchronization bus, wherein the input terminals are connected to the synchronization bus to receive synchronization signals provided by the communication circuits,

wherein each communication circuit produces, in response to a request message from a host controller device, a data communication on the communication bus in a predetermined order with respect to data communications from other communication circuits so that the data communication from each communication circuit form a sequential data stream in response to the request message,

wherein the predetermined order is determined by the synchronization signals provided by the communication circuits,

wherein each synchronization signal is transmitted on the synchronization bus by a respective communication circuit in response to the respective communication circuit producing the data communication,

wherein the plurality of communication circuits includes a first communication circuit producing a first data communication and a synchronization message,

wherein the data stream comprises:

the first data communication; and

the synchronization message before the first data communication.

2. The system of claim 1 wherein the input terminals are coupled to the communication bus to allow the communication circuit to read messages from the communication bus.

3. The system of claim 2 wherein the input terminal and the output driver of each communication circuit share a common connection to the communication bus.

4. The system of claim 1 wherein two or more of the communication circuits are situated in a same package.

5. The system of claim 4 wherein all the communication circuits are situated in the same package.

6. The system of claim 1 wherein the synchronization bus is internal to a package containing one or more of the communication circuits.

7. The system of claim 1 wherein at least a portion of the synchronization bus is external to a package containing one or more communication circuits.

8. The system of claim 1 wherein the synchronization bus is a common bus.

9. The system of claim 1 wherein the synchronization bus is a daisy-chain bus.

10. The system of claim 1 wherein the communication circuits transmit the data communications in response to synchronization signals received from the synchronization bus.

11. The system of claim 1 wherein one or more of the communication circuits produces an error check message,

wherein the data stream includes the error check message.

12. The system of claim 11 wherein the error check message is generated based on all the data communications in the data stream.

13. The system of claim 12 wherein the error check message follows one or more of the data communications in the data stream.

14. The system of claim 13 wherein the error check message is generated at the end of the data stream.

15. The system of claim 1 wherein the communication circuits communicate on the bus according to a SENT protocol.

16. The system of claim 1 wherein each communication circuit comprises a magnetic field sensor.

17. The system of claim 1 wherein the data communications from each communication circuit form a time-contiguous data stream.

18. A system comprising:

a communication bus;

a plurality of communication circuits each having an output driver coupled to the communication bus and each having an input terminal; and

a synchronization bus, wherein the input terminals are connected to the synchronization bus to receive synchronization signals,

wherein each communication circuit produces, in response to a request message from a host controller device, a data communication on the communication bus in a predetermined order with respect to data communications from other communication circuits so that the data communication from each communication circuit form a sequential data stream in response to the request,

wherein the plurality of communication circuits includes a first communication circuit producing a first data communication and a synchronization message,

wherein the communications circuits are synchronized in the predetermined order using the synchronization signals in response to the synchronization message, and

wherein the data stream comprises:

the first data communication; and

the synchronization message before the first data communication,

wherein each synchronization signal is transmitted on the synchronization bus by a respective communication circuit in response to the respective communication circuit producing the data communication.

19. The system of claim 18 wherein one synchronization message is produced at the beginning of the data stream.

20. The system of claim 18 wherein the data stream comprises multiple synchronization messages, each preceding a data communication in the data stream.

21. A communication circuit comprising:

an output driver coupled to a communication bus;

an input terminal configured to receive a first synchronization signal from another communication circuit, the input terminal being coupled to a synchronization bus configured to receive synchronization signals; and

a first communication circuitry configured to:

produce, in response to the first synchronization signal, a first data communication on the communication bus in a predetermined order with respect to data communication from other communication circuits so that the first data communication is generated as a portion of a sequential data stream;

synchronize the first data communication with respect to the data communication from the other communication circuits in response to the first synchronization signal received at the input terminal; and

transmit a second synchronization signal in response to the first communication circuitry producing the first data communication;

wherein the first synchronization signal is transmitted by a second communication circuit in response to the second communication circuit producing a second data communication as a portion of the sequential data stream,

wherein the second data communication produced by the second communication circuit is produced in response to a request message from a host controller device,

wherein the data stream comprises:

the second data communication; and

a synchronization message before the second data communication.

22. The communication circuit of claim 21 wherein the output driver and the input terminal are coupled to the same communication bus.

23. A method of communicating data from multiple communication circuits operating on a communication bus, the method comprising:

receiving, on a communication bus from a host controller device, a request message by a plurality of communication circuits operating on the communication bus, the plurality of communication circuits comprising a first communication circuit;

receiving, on a synchronization bus by the plurality of communication circuits, synchronization signals to synchronize responses of the plurality of communication circuits; and

in response to receiving the request message, transmitting, by each of the communication circuits, a communication message in a predetermined order with respect to data communications from other communication circuits, wherein the communication messages communicated by the communication circuits form a sequential data stream on the communication bus;

producing, by the first communication circuit, a first communication message and a synchronization message, wherein the data stream comprises the first communication message and the synchronization message before the first data communication,

wherein the transmitting, by each of the communication circuits, comprises:

determining the predetermined order using the synchronization signals provided by the communication circuits; and

transmitting a synchronization signal by a communication circuit in response to the communication circuit producing the communication message.

Assignments (6)
RELEASE OF SECURITY INTEREST IN PATENTS AT REEL 053957/FRAME 0874 Recorded Nov 1, 2023
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH, AS COLLATERAL AGENT
To: ALLEGRO MICROSYSTEMS, LLC
Reel/Frame 065420/0572 →
RELEASE OF SECURITY INTEREST IN PATENTS (R/F 053957/0620) Recorded Jun 22, 2023
From: MIZUHO BANK, LTD., AS COLLATERAL AGENT
To: ALLEGRO MICROSYSTEMS, LLC
Reel/Frame 064068/0360 →
PATENT SECURITY AGREEMENT Recorded Jun 22, 2023
From: ALLEGRO MICROSYSTEMS, LLC
To: MORGAN STANLEY SENIOR FUNDING, INC., AS THE COLLATERAL AGENT
Reel/Frame 064068/0459 →
PATENT SECURITY AGREEMENT Recorded Oct 1, 2020
From: ALLEGRO MICROSYSTEMS, LLC
To: MIZUHO BANK LTD., AS COLLATERAL AGENT
Reel/Frame 053957/0620 →
PATENT SECURITY AGREEMENT Recorded Oct 1, 2020
From: ALLEGRO MICROSYSTEMS, LLC
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH, AS COLLATERAL AGENT
Reel/Frame 053957/0874 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 12, 2018
From: KOZOMORA, NEVENKA; VREELAND, RICHARD
To: ALLEGRO MICROSYSTEMS, LLC
Reel/Frame 045171/0620 →
Continuity (1)
Related Publication 20190278737A1 · Sep 12, 2019
Cited By (4)
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