Stress isolation for silicon photonic applications
Techniques of minimizing or eliminating stresses in silicon photonic integrated circuits (Si-PICs) and in semiconductor packages having one or more Si-PICs (Si-PIC packages) are described. An Si-PIC or an Si-PIC package includes a stress minimization solution that assists with filtering out stresses by selectively isolating photonic and/or electronic devices, by isolating components or devices in an Si-PIC or an Si-PIC package that are sources of stress, or by isolating an Si-PIC in an Si-PIC package. The stress minimization solution may include strategically placed cavities and a stage that assist with minimizing or preventing transfer of stress to one or more photonic and/or electronic devices in an Si-PIC or an Si-PIC package.
1. A semiconductor package, comprising:
a silicon photonic integrated circuit (Si-PIC); and
a package substrate comprising one or more cavities, a stage, and one or more exposed top surfaces, wherein a portion of the stage overhangs one or more of the one or more cavities, and wherein the Si-PIC is on the stage and coupled to the stage via one or more interconnect structures.
2. The semiconductor package of claim 1 , wherein the one or more interconnect structures comprise one or more of bumps, microbumps, pillars, an underfill composition, an epoxy resin, and a combination thereof.
3. The semiconductor package of claim 1 , wherein the package substrate further comprises one or more electronic components positioned on the one or more exposed top surfaces of the substrate.
4. The semiconductor package of claim 1 , wherein the Si-PIC comprises one or more of:
one or more photonic devices; and
one or more electronic devices.
5. A semiconductor package, comprising:
a silicon photonic integrated circuit (Si-PIC); and
a package substrate comprising one or more cavities, a stage, and an exposed top surface, wherein a portion of the stage overhangs one or more of the one or more cavities, wherein the Si-PIC is on the stage, wherein an electrical component is on the exposed top surface, and wherein the Si-PIC and the electrical component are coupled to the package substrate via one or more interconnect structures.
6. The semiconductor package of claim 5 , wherein the one or more interconnect structures comprise one or more of bumps, microbumps, pillars, an underfill composition, an epoxy resin, and a combination thereof.
7. The semiconductor package of claim 5 , wherein the package substrate further comprises a second exposed top surface, wherein a second electronic component is on the second exposed top surface and coupled to the package substrate via the one or more interconnect structures.
8. The semiconductor package of claim 5 , wherein the Si-PIC comprises one or more of:
one or more photonic devices; and
one or more electronic devices.
9. A silicon photonic integrated circuit (Si-PIC), comprising:
one or more exposed top surfaces;
one or more cavities; and
a stage, wherein a portion of the stage overhangs one or more of the one or more cavities, and wherein the stage comprises one or more interconnect structures positioned thereon.
10. The Si-PIC of claim 9 , wherein the one or more cavities and the stage are positioned in or on an active silicon layer of the Si-PIC.
11. The Si-PIC of claim 9 , wherein the one or more interconnect structures comprise one or more of bumps, microbumps, pillars, an underfill composition, an epoxy resin, and a combination thereof.
12. The Si-PIC of claim 11 , wherein a package substrate is coupled to the one or more interconnect structures.
13. The Si-PIC of claim 9 , wherein the Si-PIC further comprises one or more of:
one or more photonic devices positioned on the one or more exposed top surfaces; and
one or more electronic devices.
14. A silicon photonic integrated circuit (Si-PIC), comprising:
one or more cavities;
a stage, wherein a portion of the stage overhangs one or more of the one or more cavities; and
one or more exposed top surfaces, wherein one of the one or more exposed top surfaces comprises one or more interconnect structures positioned thereon.
15. The Si-PIC of claim 14 , wherein the one or more cavities and the stage are positioned in or on an active silicon layer of the Si-PIC.
16. The Si-PIC of claim 14 , wherein the one or more interconnect structures comprise one or more of bumps, microbumps, pillars, an underfill composition, an epoxy resin, and a combination thereof.
17. The Si-PIC of claim 16 , wherein a package substrate is coupled to the one or more interconnect structures.
18. The Si-PIC of claim 14 , wherein the Si-PIC further comprises one or more of:
one or more photonic devices positioned on another one of the one or more exposed top surfaces or on the stage; and
one or more electronic devices.