IP Library › Granted Patent US 10,748,891
Granted Patent B1
US 10,748,891 · App. 16/274,129 · Granted Aug 18, 2020

Electrostatic discharge (ESD) robust transistor

Inventor: Ranadeep Dutta (Del Mar, CA)
Assignee: QUALCOMM Incorporated
H01L27/0266H01L29/0696H01L29/66484H01L29/66492H01L29/7831H01L29/7835
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Quick Facts
Patent No.
US 10,748,891
App. No.
16/274,129
Granted
Aug 18, 2020
Kind
B1
Abstract

A multi-gate active device includes a source region coupled to source contacts and a first drain region coupled to first drain contacts. The multi-gate active device also includes a first meshed silicide stop on the first drain region. The first meshed silicide stop surrounds the first drain contacts. The multi-gate active device further includes a first gate over a first channel between the source region and the first drain region.

Claims (36)

1. A multi-gate active device comprising:

a source region coupled to source contacts;

a first drain region coupled to first drain contacts;

a first meshed silicide stop on the first drain region and surrounding the first drain contacts;

a first gate on a first channel between the source region and the first drain region;

a second drain region coupled to second drain contacts;

a second meshed silicide stop on the second drain region and surrounding the second drain contacts;

a second gate on a second channel between the source region and the second drain region; and

a third gate adjacent to the first drain region, the third gate on a third channel between the first drain region and another source region, the first drain region between the first gate and the third gate, the source region between the first gate and the second gate, a first spacing between the first gate and the second gate being different than a second spacing between the first gate and the third gate.

2. A method of making a multi-gate active device comprising:

creating a source region coupled to source contacts;

creating a first drain region coupled to first drain contacts through a drain silicide region on the first drain region;

depositing a first meshed silicide stop on the first drain region and surrounding the first drain contacts;

fabricating a first gate on a first channel between the source region and the first drain region;

depositing a gate silicide region on the first gate, in which the first meshed silicide stop comprises a predefined silicide stop length between the gate silicide region and the drain silicide region;

creating a second drain region coupled to second drain contacts;

depositing a second meshed silicide stop on the second drain region and surrounding the second drain contacts;

fabricating a second gate on a second channel between the source region and the second drain region; and

fabricating a third gate adjacent to the first drain region, the third gate on a third channel between the first drain region and another source region, the first drain region between the first gate and the third gate, the source region between the first gate and the second gate, a first spacing between the first gate and the second gate being different than a second spacing between the first gate and the third gate.

3. The method of claim 2 , further comprising fabricating the source contacts on a silicide region of the source region.

4. The method of claim 2 , in which making the multi-gate active device comprises making a shunt switch.

5. A multi-gate active device comprising:

a source region coupled to source contacts;

a first drain region coupled to first drain contacts;

means for protecting the first drain region from silicidation, the protecting means surrounding the first drain contacts;

a first gate on a first channel between the source region and the first drain region;

a second drain region coupled to second drain contacts;

a meshed silicide stop on the second drain region and surrounding the second drain contacts;

a second gate on a second channel between the source region and the second drain region; and

a third gate adjacent to the first drain region, the third gate on a third channel between the first drain region and another source region, the first drain region between the first gate and the third gate, the source region between the first gate and the second gate, a first spacing between the first gate and the second gate being different than a second spacing between the first gate and the third gate.

6. The multi-gate active device of claim 5 , in which the protecting means overlaps a portion of the first gate.

7. The multi-gate active device of claim 5 , in which spacing between gates of the multi-gate active device is asymmetric.

8. The multi-gate active device of claim 5 , further comprising a predefined length of the protecting means between the first gate and a silicide region of the first drain region.

9. The multi-gate active device of claim 8 , in which the first drain contacts are on the silicide region of the first drain region.

10. The multi-gate active device of claim 5 , in which the source contacts are on a silicide region of the source region.

11. The multi-gate active device of claim 5 comprising a shunt switch.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 8, 2019
From: DUTTA, RANADEEP
To: QUALCOMM INCORPORATED
Reel/Frame 048823/0545 →