Shift register unit, method of driving shift register unit, gate driving circuit and display device

1. A shift register unit, comprising an input circuit, a first pull-up node reset circuit, and an output circuit;

wherein the input circuit comprises an input terminal, and is configured to control an level of a pull-up node to a first level in response to an input signal of the input terminal, and thereafter control a level of a first node to a second level under control of a level of a pull-down node, in which the first node is in a current path for controlling the level of the pull-up node;

the first pull-up node reset circuit is configured to reset the pull-up node in response to a first reset signal; and

the output circuit is configured to output a clock signal to an output terminal under control of the level of the pull-up node;

the input circuit comprises a first input sub-circuit, a second input sub-circuit, and a first node control sub-circuit;

the first input sub-circuit is configured to control the level of the first node to the first level in response to the input signal;

the second input sub-circuit is configured to control the level of the pull-up node to the first level in response to the input signal; and

the first node control sub-circuit is configured to control the level of the first node to the second level under control of the level of the pull-down node.

2. The shift register unit according to claim 1 , wherein the first input sub-circuit comprises:

a first transistor, in which a gate electrode of the first transistor is configured to be connected to the input terminal to receive the input signal, a first electrode of the first transistor is configured to be connected to a first voltage terminal to receive a first voltage, and a second electrode of the first transistor is configured to be connected to the first node;

the second input sub-circuit comprises: a second transistor, in which a gate electrode of the second transistor is configured to be connected to the input terminal to receive the input signal, a first electrode of the second transistor is configured to be connected to the first node, and a second electrode of the second transistor is configured to be connected to the pull-up node; and

the first node control sub-circuit comprises: a third transistor, in which a gate electrode of the third transistor is configured to be connected to the pull-down node, a first electrode of the third transistor is configured to be connected to the first node, and a second electrode of the third transistor is configured to be connected to a second voltage terminal to receive a second voltage.

3. The shift register unit according to claim 1 , further comprising a pull-down circuit, a pull-down control circuit, a pull-up node noise reduction circuit, and an output noise reduction circuit;

wherein the pull-down circuit is configured to control the level of the pull-down node under control of the level of the pull-up node and a level of a pull-down control node;

the pull-down control circuit is configured to control the level of the pull-down control node under control of the level of the pull-up node;

the pull-up node noise reduction circuit is configured to perform noise reduction on the pull-up node under control of the level of the pull-down node; and

the output noise reduction circuit is configured to perform noise reduction on the output terminal under control of the level of the pull-down node.

4. The shift register unit according to claim 3 , wherein the pull-down circuit comprises an eighth transistor and a ninth transistor;

a gate electrode of the eighth transistor is configured to be connected to the pull-down control node, a first electrode of the eighth transistor is configured to be connected to a clock signal terminal to receive the clock signal, and a second electrode of the eighth transistor is configured to be connected to the pull-down node; and

a gate electrode of the ninth transistor is configured to be connected to the pull-up node, a first electrode of the ninth transistor is configured to be connected to the pull-down node, and a second electrode of the ninth transistor is configured to be connected to a second voltage terminal to receive a second voltage.

5. The shift register unit according to claim 3 , wherein the pull-down control circuit comprises a tenth transistor and an eleventh transistor;

a gate electrode of the tenth transistor is connected to a first electrode of the tenth transistor and configured to be connected to a clock signal terminal to receive the clock signal, and a second electrode of the tenth transistor is configured to be connected to the pull-down control node; and

a gate electrode of the eleventh transistor is configured to be connected to the pull-up node, a first electrode of the eleventh transistor is configured to be connected to the pull-down control node, and a second electrode of the eleventh transistor is configured to be connected to a second voltage terminal to receive a second voltage.

6. The shift register unit according to claim 3 , wherein the pull-up node noise reduction circuit comprises a twelfth transistor; and

a gate electrode of the twelfth transistor is configured to be connected to the pull-down node, a first electrode of the twelfth transistor is configured to be connected to the pull-up node, and a second electrode of the twelfth transistor is configured to be connected to a second voltage terminal to receive a second voltage.

7. The shift register unit according to claim 3 , wherein the output noise reduction circuit comprises a thirteenth transistor; and

a gate electrode of the thirteenth transistor is configured to be connected to the pull-down node, a first electrode of the thirteenth transistor is configured to be connected to the output terminal, and a second electrode of the thirteenth transistor is configured to be connected to a second voltage terminal to receive a second voltage.

8. The shift register unit according to claim 1 , wherein the first pull-up node reset circuit is further configured to control a level of a second node to the second level under control of the level of the pull-down node, and the second node is in a reset path for resetting the pull-up node.

9. The shift register unit according to claim 8 , wherein the first pull-up node reset circuit comprises a first reset sub-circuit, a second reset sub-circuit, and a second node control sub-circuit;

the first reset sub-circuit is configured to reset the second node in response to the first reset signal;

the second reset sub-circuit is configured to reset the pull-up node in response to the first reset signal; and

the second node control sub-circuit is configured to control the level of the second node to the second level under control of the level of the pull-down node.

10. The shift register unit according to claim 9 , wherein the first reset sub-circuit comprises:

a fourth transistor, in which a gate electrode of the fourth transistor is configured to be connected to a first reset terminal to receive the first reset signal, a first electrode of the fourth transistor is configured to be connected to a third voltage terminal to receive a third voltage, and a second electrode of the fourth transistor is configured to be connected to the second node;

the second reset sub-circuit comprises: a fifth transistor, in which a gate electrode of the fifth transistor is configured to be connected to the first reset terminal to receive the first reset signal, a first electrode of the fifth transistor is configured to be connected to the second node, and a second electrode of the fifth transistor is configured to be connected to the pull-up node; and

the second node control sub-circuit comprises: a sixth transistor, in which a gate electrode of the sixth transistor is configured to be connected to the pull-down node, a first electrode of the sixth transistor is configured to be connected to the second node, and a second electrode of the sixth transistor is configured to be connected to a second voltage terminal to receive a second voltage.

11. A method of driving the shift register unit according to claim 8 , wherein the input signal and the first reset signal are exchanged with each other, and the method comprises:

in a first phase, the first pull-up node reset circuit controls the level of the pull-up node to the first level in response to the input signal, and the output circuit outputs a third level of the clock signal to the output terminal;

in a second phase, the output circuit outputs a fourth level of the clock signal to the output terminal;

in a third phase, the input circuit resets the pull-up node under control of the first reset signal; and

in a fourth phase, the first pull-up node reset circuit controls the level of the second node to the second level under control of the level of the pull-down node.

12. The shift register unit according to claim 1 , wherein the output circuit comprises a seventh transistor and a first capacitor;

a gate electrode of the seventh transistor is configured to be connected to the pull-up node, a first electrode of the seventh transistor is configured to be connected to a clock signal terminal to receive the clock signal, and a second electrode of the seventh transistor is configured to be connected to the output terminal; and

a first electrode of the first capacitor is configured to be connected to the gate electrode of the seventh transistor, and a second electrode of the first capacitor is configured to be connected to the second electrode of the seventh transistor.

13. The shift register unit according to claim 1 , further comprising a second pull-up node reset circuit;

wherein the second pull-up node reset circuit is configured to reset the pull-up node in response to a second reset signal.

14. The shift register unit according to claim 13 , wherein the second pull-up node reset circuit comprises a fourteenth transistor; and

a gate electrode of the fourteenth transistor is configured to be connected to a second reset terminal to receive the second reset signal, a first electrode of the fourteenth transistor is configured to be connected to the pull-up node, and a second electrode of the fourteenth transistor is configured to be connected to a second voltage terminal to receive a second voltage.

15. The shift register unit according to claim 1 , further comprising an output reset circuit;

wherein the output reset circuit is configured to reset the output terminal in response to a second reset signal.

16. The shift register unit according to claim 15 , wherein the output reset circuit comprises a fifteenth transistor; and

a gate electrode of the fifteenth transistor is configured to be connected to a second reset terminal to receive the second reset signal, a first electrode of the fifteenth transistor is configured to be connected to the output terminal, and a second electrode of the fifteenth transistor is configured to be connected to a second voltage terminal to receive a second voltage.

17. A gate driving circuit, comprising the shift register unit according to claim 1 .

18. A display device, comprising the gate driving circuit according to claim 17 .

19. A method of driving the shift register unit according to claim 1 , comprising:

in a first phase, the input circuit controlling the level of the pull-up node to the first level in response to the input signal, and the output circuit outputting a third level of the clock signal to the output terminal;

in a second phase, the output circuit outputting a fourth level of the clock signal to the output terminal;

in a third phase, the first pull-up node reset circuit resetting the pull-up node under control of the first reset signal; and

in a fourth phase, the input circuit controlling the level of the first node to the second level under control of the level of the pull-down node.