High bandwidth die to die interconnect with package area reduction
Package structure with folded die arrangements and methods of fabrication are described. In an embodiment, a package structure includes a first die and vertical interposer side-by-side. A second die is face down on an electrically connected with the vertical interposer, and a local interposer electrically connects the first die with the vertical interposer.
1. A package structure comprising:
a first wiring layer including a first side and a second side opposite the first side;
a first die and a vertical interposer side-by-side on the first side of the first wiring layer, wherein the vertical interposer includes electrical interconnects from a first side of the vertical interposer coupled with the first side of the first wiring layer to a second side of the vertical interposer opposite the first side of the vertical interposer;
a second die face down on and electrically connected with the second side of the vertical interposer; and
a local interposer on the second side of the first wiring layer and in electrical connection with the first die and the vertical interposer;
wherein the second die occupies a larger area than both the vertical interposer and the local interposer.
2. The package structure of claim 1 , wherein the local interposer includes a plurality of terminals on a first side of the local interposer that is coupled with the second side of the first wiring layer, and the local interposer does not include a terminal on a second side of the local interposer opposite the first side of the local interposer.
3. The package structure of claim 1 , wherein the first die occupies a larger area than the second die.
4. The package structure of claim 3 , wherein the first die and the second die comprise split logic.
5. The package structure of claim 3 , wherein first transistors of the first die are formed with a smaller processing node than second transistors of the second die.
6. The package structure of claim 1 , further comprising a mechanical chiplet attached to the first die laterally adjacent to the second die.
7. The package structure of claim 1 , wherein the vertical interposer is hybrid bonded with the second die.
8. The package structure of claim 1 , wherein solder bumps electrically connect the vertical interposer with the second die.
9. A package structure comprising:
a first wiring layer including a first side and a second side opposite the first side;
a first die and a vertical interposer side-by-side on the first side of the first wiring layer, wherein the vertical interposer includes electrical interconnects from a first side of the vertical interposer coupled with the first side of the first wiring layer to a second side of the vertical interposer opposite the first side of the vertical interposer;
a second die face down on and electrically connected with the second side of the vertical interposer;
a local interposer on the second side of the first wiring layer and in electrical connection with the first die and the vertical interposer;
a first molding compound encapsulating the first die, the vertical interposer, and the second die; and
a second molding compound encapsulating the local interposer on the second side of the first wiring layer.
10. The package structure of claim 9 , further comprising a mechanical chiplet attached to the first die laterally adjacent to the second die.
11. The package structure of claim 9 , further comprising a first plurality of conductive pillars extending from the first wiring layer and through the first molding compound.
12. The package structure of claim 9 , wherein first transistors of the first die are formed with a smaller processing node than second transistors of the second die.
13. The package structure of claim 9 , further comprising a second plurality of conductive pillars extending from the first wiring layer and through the second molding compound.
14. The package structure of claim 13 , further comprising a second wiring layer on the second molding compound and connected to the second plurality of conductive pillars.
15. The package structure of claim 14 , wherein the second wiring layer is on a planarized surface including the second molding compound, the second plurality of conductive pillars, and the local interposer.
16. The package structure of claim 13 , further comprising a second package on and in electrical connection with the first plurality of conductive pillars.
17. The package structure of claim 13 , further comprising a plurality of solder bumps that electrically connect the second wiring layer to a package routing substrate.
18. A method of forming a package structure comprising:
placing a second die and mechanical chiplet on a carrier substrate;
bonding a vertical interposer to the second die;
placing a first die on the second die and the mechanical chiplet;
encapsulating the second die, the mechanical chiplet, the vertical interposer, and the first die in a first molding compound;
mounting a local interposer on and in electrical connection with the vertical interposer and the first die; and
encapsulating the local interposer in a second molding compound.
19. The method of claim 18 , wherein bonding the vertical interposer to the second die comprises hybrid bonding.
20. The method of claim 18 , wherein bonding the vertical interposer to the second die comprises solder bumping.