Beaded fin transistor
Techniques are disclosed for forming a beaded fin transistor. As will be apparent in light of this disclosure, a transistor including a beaded fin configuration may be formed by starting with a multilayer finned structure, and then selectively etching one or more of the layers to form at least one necked (or relatively narrower) portion, thereby forming a beaded fin structure. The beaded fin transistor configuration has improved gate control over a finned transistor configuration having the same top down area or footprint, because the necked/narrower portions increase gate surface area as compared to a non-necked finned structure, such as finned structures used in finFET devices. Further, because the beaded fin structure remains intact (e.g., as compared to a gate-all-around (GAA) transistor configuration where nanowires are separated from each other), the parasitic capacitance problems caused by GAA transistor configurations are mitigated or eliminated.
1. An integrated circuit including at least one transistor, the integrated circuit comprising:
a gate structure including a gate dielectric and a gate electrode; and
a fin below the gate structure, the fin also between portions of the gate structure, the fin including
a first layer including a first semiconductor material, the first layer having upper, middle, and lower sections that form a continuous portion of the first layer that is between the portions of the gate structure, with the middle section below the upper section and above the lower section, wherein a smallest horizontal width of the middle section is at least 2 nanometers (nm) less than each of (i) a smallest horizontal width of the upper section and (ii) a smallest horizontal width of the lower section, and
a second layer in contact with the first layer, the second layer including a second semiconductor material compositionally different from the first semiconductor material, the second layer having a horizontal width that is higher than the smallest horizontal width of the middle section of the first layer.
2. The integrated circuit of claim 1 , wherein the smallest horizontal width of the middle section is in the range of 2 to 15 nanometers.
3. The integrated circuit of claim 1 , wherein the horizontal width of the second layer is in the range of 4 to 30 nanometers.
4. The integrated circuit of claim 1 , wherein the smallest horizontal width of the middle section is at least 2 nanometers less than the horizontal width of the second layer.
5. The integrated circuit of claim 1 , wherein the horizontal width of the second layer is at least 2 times the smallest horizontal width of the middle section.
6. The integrated circuit of claim 1 , wherein at least one of the first or second layers includes group III-V semiconductor material.
7. The integrated circuit of claim 1 , wherein at least one of the first or second layers includes group IV semiconductor material.
8. The integrated circuit of claim 1 , wherein the first semiconductor material has a bandgap of at least 0.3 electron volts (eV) greater than the second semiconductor material.
9. The integrated circuit of claim 1 , wherein the second semiconductor material has a bandgap of at least 0.3 electron volts (eV) greater than the first semiconductor material.
10. The integrated circuit of claim 1 , wherein the second semiconductor material includes indium, gallium, and arsenic.
11. The integrated circuit of claim 1 , wherein the first semiconductor material includes arsenic and one of indium or gallium.
12. The integrated circuit of claim 1 , wherein the first and second layers each include a vertical thickness in the range of 2 to 20 nanometers.
13. The integrated circuit of claim 1 , further comprising a third layer below the fin, the third layer including a third semiconductor material compositionally different from both of the first and second semiconductor materials.
14. The integrated circuit of claim 1 , further comprising a source region and a drain region, at least a portion of the fin between the source and drain regions.
15. A computing system comprising the integrated circuit of claim 1 .
16. An integrated circuit including at least one transistor, the integrated circuit comprising:
a gate structure including a gate dielectric and a gate electrode; and
a fin below the gate structure, the fin also between portions of the gate structure, the fin including
a first layer including a first semiconductor material, the first layer having upper, middle, and lower sections, with the middle section between the upper and lower sections, wherein a minimum horizontal width of the middle section is less than each of (i) a minimum horizontal width of the upper section and (ii) a minimum horizontal width of the lower section,
a second layer in contact with the first layer, the second layer including a second semiconductor material compositionally different from the first semiconductor material, the second layer having a minimum horizontal width that is at least 2 nanometers (nm) higher than the minimum horizontal width of the middle section,
a third layer in contact with the second layer, the third layer including the first semiconductor material, the third layer having a minimum horizontal width that is less than the minimum horizontal width of the second layer, and
a fourth layer in contact with the third layer, the fourth layer including the second semiconductor material.
17. The integrated circuit of claim 16 , wherein the minimum horizontal widths of the middle section and the third layer are in the range of 2 to 15 nanometers, and wherein the minimum horizontal width of the second layer is in the range of 4 to 30 nanometers.
18. The integrated circuit of claim 16 , wherein the first semiconductor material includes arsenic and one of indium or gallium, and the second semiconductor material includes indium, gallium, and arsenic.
19. An integrated circuit including at least one transistor, the integrated circuit comprising:
a gate structure including a gate dielectric and a gate electrode; and
a fin below the gate structure and also at least in part between portions of the gate structure, the fin including
a first layer including a first semiconductor material, the first layer having a first horizontal width,
a second layer underneath the first layer, the second layer including a second semiconductor material compositionally different from the first semiconductor material, the second layer having a second minimum horizontal width, the second minimum horizontal width less than the first horizontal width by at least 2 nanometers (nm),
a third layer underneath the second layer, the third layer including the first semiconductor material of the first layer, and
a fourth layer directly underneath the third layer and compositionally different from the third layer, wherein a horizontal width of each of the third and fourth layers are at least 2 nm greater than the second minimum horizontal width of the second layer.
20. The integrated circuit of claim 19 , wherein at least a section of the fourth layer is between portions of an insulation material.