Gain and sensitivity in a Gilbert switch stage
A power detector with a main transconductance stage and a Gilbert switch stage coupled to one another. Current sources are coupled between the main transconductance and the Gilbert switch stages. Each of the current sources is configured to generate a cascoded PMOS trickle current under the control of a DAC to control the effective voltage of the Gilbert switch stage. This mitigates the DC offsets resulting in enhanced sensitivity of the Gilbert switch stage. An increase in the conversion gain of a system using a Gilbert switch stage, for a given LO swing, is therefore obtained for a very small increase in DC power.
1. An apparatus, comprising:
a main transconductance (MT) stage having an MT differential input port and first and second MT output paths;
a Gilbert switch (GS) stage, coupled to the first and second MT output paths, comprising a GS differential input port and a GS differential output port;
a first current source having an output coupled to the first MT output path; and
a second current source having an output coupled to the second MT output path,
wherein at least one of the first and second current sources is configured to:
generate a cascoded trickle current into the respective first or second output path as a function of an output of a DAC.
2. The apparatus of claim 1 , wherein the at least one current source comprises:
first and second transistors coupled in series between a supply rail and the respective current source output; and
a DAC having an output coupled to a node between the first and second transistors.
3. The apparatus of claim 1 , wherein the GS stage comprises:
cross-coupled pairs of transistors configured to form the GS differential input port and the GS differential output port.
4. The apparatus of claim 1 , wherein each of the transistors in the GS stage is a FET.
5. The apparatus of claim 1 , wherein each of the transistors in the GS stage is a bi-polar transistor.
6. The apparatus of claim 1 , wherein an output of the DAC can source or sink current.
7. An apparatus, comprising:
a main transconductance (MT) stage having an MT differential input port and first and second MT output paths;
a Gilbert switch (GS) stage, coupled to the first and second MT output paths, comprising a GS differential input port and a GS differential output port;
a first current source having an output coupled to the first MT output path; and
a second current source having an output coupled to the second MT output path,
wherein each of the first and second current sources is configured to generate a respective first and second trickle current at the respective current source output and introduce the generated first and second trickle current into the respective first and second MT output path, and
wherein each of the first and second current sources comprises:
first and second PMOS transistors coupled in series between a supply rail and the respective output; and
a DAC having an output coupled to a node between the first and second transistors.
8. The apparatus of claim 7 , wherein the GS stage comprises:
first and second differential pairs of transistors, wherein common sources of the first and second differential pairs of transistors are coupled to the first and second MT output paths,
wherein inputs of the first and second differential pairs of transistors are cross-coupled to form the GS differential input port, and
wherein outputs of the differential pairs of transistors are cross-coupled to form the GS differential output port.
9. The apparatus of claim 7 , wherein each of the transistors in the GS stage is a FET.
10. The apparatus of claim 7 , wherein each of the transistors in the GS stage is a bi-polar transistor.
11. The apparatus of claim 7 , wherein an output of the DAC can source or sink current.
12. The apparatus of claim 7 , wherein each of the first and second trickle currents is a cascoded PMOS trickle current.
13. A power detector, comprising:
an input differential amplifier having a first differential input port and first and second output paths;
an output differential amplifier having first and second differential pairs of transistors wherein common sources of the differential pairs of transistors are coupled to the first and second output paths, inputs of the differential pairs of transistors are cross-coupled to form a second differential input port and outputs of the differential pairs of transistors are cross-coupled to form a first differential output port;
a load coupled to the first differential output port;
a first current source having an output coupled to the first output path;
a second current source having an output coupled to the second output path,
wherein each of the first and second current sources is configured to generate a respective first and second trickle current at the respective current source output and introduce the generated first and second trickle current into the respective first and second output path, and
wherein each of the first and second current sources comprises:
first and second transistors coupled in series between a supply rail and the respective current source output; and
a DAC having an output coupled to a node between the first and second transistors.
14. The power detector of claim 13 , wherein the output differential amplifier comprises a Gilbert switch stage.
15. The power detector of claim 13 , wherein each of the first and second transistors in the first and second current sources is a PMOS transistor.
16. The power detector of claim 15 , wherein each of the first and second trickle currents is a cascoded PMOS trickle current.
17. The power detector of claim 13 , wherein an output of the DAC can source or sink current.
18. The power detector of claim 13 , wherein each of the transistors in the output differential amplifier is a FET.
19. The power detector of claim 13 , wherein each of the transistors in the output differential amplifier is a bi-polar transistor.