Netlist partitioning for designs targeting a data processing engine array

1. A method for compiling, the method comprising:

by a processor-based system:

obtaining a netlist of an application, the netlist containing program nodes and respective edges between the program nodes, the application to be implemented on a device comprising an array of data processing engines;

partitioning the netlist into a plurality of partitions;

for each of the plurality of partitions:

generating a global mapping of the program nodes based on a representation of the array of data processing engines and using an integer linear programming (ILP) algorithm;

generating a detailed mapping of the program nodes based on the global mapping; and

translating the detailed mapping for each of the plurality of partitions to a file.

2. The method of claim 1 , wherein partitioning the netlist comprises:

reducing a solution space by constraining the netlist to a portion of the array of data processing engines based on a target utilization ratio.

3. The method of claim 1 , wherein partitioning the netlist comprises:

performing recursive bi-partitioning of the netlist to generate the plurality of partitions until each of the plurality of partitions comprises a leaf partition, the leaf partition being non-partitionable based on one or more metrics.

4. The method of claim 3 , wherein the one or more metrics comprises at least one of a utilization metric, a size metric, and a cost metric.

5. The method of claim 3 , wherein performing the recursive bi-partitioning comprises cutting the netlist into two portions that minimizes a sum of weights of the edges.

6. The method of claim 5 , wherein the two portions of the netlist are adjusted based on resource utilization of each of the two portions.

7. The method of claim 5 , wherein each of the edges comprises a stream or a memory connection, and wherein edges that are streams have a smaller weight than edges that are memory connections.

8. A non-transitory computer readable medium having stored thereon instruction that when executed by a processor cause the processor to perform a method for compiling, the method comprising:

obtaining a netlist of an application, the netlist containing program nodes and respective edges between the program nodes, the application to be implemented on a device comprising an array of data processing engines;

partitioning the netlist into a plurality of partitions;

for each of the plurality of partitions:

generating a global mapping of the program nodes based on a representation of the array of data processing engines and using an integer linear programming (ILP) algorithm;

generating a detailed mapping of the program nodes based on the global mapping; and

translating the detailed mapping for each of the plurality of partitions to a file.

9. The non-transitory computer readable medium of claim 8 , wherein partitioning the netlist comprises:

reducing a solution space by constraining the netlist to a portion of the array of data processing engines based on a target utilization ratio.

10. The non-transitory computer readable medium of claim 8 , wherein partitioning the netlist comprises:

performing recursive bi-partitioning of the netlist to generate the plurality of partitions until each of the plurality of partitions comprises a leaf partition, the leaf partition being non-partitionable based on one or more metrics.

11. The non-transitory computer readable medium of claim 10 , wherein the one or more metrics comprises at least one of a utilization metric, a size metric, and a cost metric.

12. The non-transitory computer readable medium of claim 10 , wherein performing the recursive bi-partitioning comprises cutting the netlist into two portions that minimizes a sum of weights of the edges.

13. The non-transitory computer readable medium of claim 12 , wherein the two portions of the netlist are adjusted based on resource utilization of each of the two portions.

14. The non-transitory computer readable medium of claim 12 , wherein each of the edges comprises a stream or a memory connection, and wherein edges that are streams have a smaller weight than edges that are memory connections.

15. A design system comprising:

a processor; and

a memory coupled to the processor, the memory storing instruction code, the processor being configured to execute the instruction code to perform:

obtaining a netlist of an application, the netlist containing program nodes and respective edges between the program nodes, the application to be implemented on a device comprising an array of data processing engines;

partitioning the netlist into a plurality of partitions;

for each of the plurality of partitions:

generating a global mapping of the program nodes based on a representation of the array of data processing engines and using an integer linear programming (ILP) algorithm;

generating a detailed mapping of the program nodes based on the global mapping; and

translating the detailed mapping for each of the plurality of partitions to a file.

16. The design system of claim 15 , wherein the partitioning comprises:

reducing a solution space by constraining the netlist to a portion of the array of data processing engines based on a target utilization ratio.

17. The design system of claim 15 , wherein the partitioning comprises:

performing recursive bi-partitioning of the netlist to generate the plurality of partitions until each of the plurality of partitions comprises a leaf partition, the leaf partition being non-partitionable based on one or more metrics.

18. The design system of claim 17 , wherein the one or more metrics comprises at least one of a utilization metric, a size metric, and a cost metric.

19. The design system of claim 17 , wherein performing the recursive bi-partitioning comprises cutting the netlist into two portions that minimizes a sum of weights of the edges.

20. The design system of claim 19 , wherein the two portions of the netlist are adjusted based on resource utilization of each of the two portions.