Sensing a memory device

1. A memory device comprising:

a memory cell array that includes a plurality of bit lines, wherein a bit line is coupled to a plurality of memory cells;

a plurality of sense amplifiers, wherein a sense amplifier is coupled to a bit line and provides a sensing current to access data from one or more memory cells of the plurality of memory cells corresponding to the bit line; and

a memory controller for controlling the plurality of sense amplifiers, the memory controller performing operations comprising:

during a pre-charging stage of a memory access cycle, providing, to a particular sense amplifier, a first voltage; and

during a sensing stage of the memory access cycle, providing, to the particular sense amplifier, a second voltage, wherein the second voltage is a non-zero voltage that is lower than the first voltage.

2. The memory device of claim 1 , wherein the first voltage drives the sensing current to access data from a target memory cell.

3. The memory device of claim 2 , wherein the sensing current includes (i) a first current provided to a plurality of memory cells coupled to a particular bit line that includes the target memory cell, and (ii) a second current provided to a capacitance circuit corresponding to the particular bit line.

4. The memory device of claim 3 , wherein the particular sense amplifier includes:

a sensing unit that generates the first current based on a first control signal received from the memory controller; and

a pre-charging unit that generates the second current based on a second control signal and a third control signal that are received from the memory controller.

5. The memory device of claim 4 , wherein the sensing unit includes:

a first transistor that provides the first voltage upon application of the first control signal to a gate of the first transistor, and provides the second voltage upon application of a fourth control signal to the gate of the first transistor.

6. The memory device of claim 4 , wherein the sensing unit includes:

a first transistor that provides the first voltage upon application of the first control signal to a gate of the first transistor; and

a second transistor that provides the second voltage upon application of a fourth control signal to a gate of the second transistor.

7. The memory device of claim 4 , wherein the pre-charging unit includes:

a first transistor that provides a third voltage upon application of the second control signal to a gate of the first transistor; and

a second transistor that provides a fourth voltage upon application of the third control signal to a gate of the second transistor,

wherein the second current is generated using the third voltage and the fourth voltage.

8. The memory device of claim 3 , wherein the capacitance circuit includes a parasitic capacitance of the particular bit line and a cross-coupling capacitance shared between the particular bit line and an adjacent bit line.

9. The memory device of claim 1 , wherein the particular sense amplifier provides the sensing current to a plurality of memory cells coupled to a particular bit line during a memory access cycle, and wherein the memory controller:

provides the first voltage to the particular sense amplifier to bias the particular bit line to a known voltage level during the pre-charging stage, and

provides the second voltage to the particular sense amplifier to limit a variation in the bias of the particular bit line within a known voltage range during the sensing stage.

10. The memory device of claim 9 , wherein a value of the second voltage is selected to maintain the bias of a particular bit line coupled to the particular sense amplifier at a known voltage level.

11. A method for sensing a memory device, the method comprising:

during a pre-charging stage of a memory access cycle, providing, by a memory controller to a particular sense amplifier of a plurality of sense amplifiers included in the memory device, a first voltage,

wherein a sense amplifier of the plurality of sense amplifiers is coupled to a bit line of a plurality of bit lines included in the memory device and provides a sensing current to access data from one or more memory cells corresponding to the bit line; and

during a sensing stage of the memory access cycle, providing, by the memory controller to the particular sense amplifier, a second voltage, wherein the second voltage is a non-zero voltage that is lower than the first voltage.

12. The method of claim 11 , wherein providing the first voltage to the particular sense amplifier comprises driving the sensing current to access data from a target memory cell.

13. The method of claim 12 , wherein the sensing current includes (i) a first current provided to a plurality of memory cells coupled to a particular bit line that includes the target memory cell, and (ii) a second current provided to a capacitance circuit corresponding to the particular bit line.

14. The method of claim 13 , further comprising:

generating, using a sensing unit included in the particular sense amplifier, the first current based on a first control signal received from the memory controller; and

generating, using a pre-charging unit included in the particular sense amplifier, the second current based on a second control signal and a third control signal that are received from the memory controller.

15. The method of claim 14 , further comprising:

providing, using a first transistor included in the sensing unit, the first voltage upon application of the first control signal to a gate of the first transistor; and

providing, using the first transistor, the second voltage upon application of a fourth control signal to the gate of the first transistor.

16. The method of claim 14 , further comprising:

providing, using a first transistor included in the sensing unit, the first voltage upon application of the first control signal to a gate of the first transistor; and

providing, using a second transistor included in the sensing unit, second voltage upon application of a fourth control signal to a gate of the second transistor.

17. The method of claim 14 , further comprising:

providing, using a first transistor included in the pre-charging unit, a third voltage upon application of the second control signal to a gate of the first transistor; and

providing, using a second transistor included in the pre-charging unit, a fourth voltage upon application of the third control signal to a gate of the second transistor,

wherein the second current is generated using the third voltage and the fourth voltage.

18. The method of claim 13 , wherein the second current is provided to a parasitic capacitance of the particular bit line and a cross-coupling capacitance shared between the particular bit line and an adjacent bit line, wherein the parasitic capacitance and the cross-coupling capacitance are included in the capacitance circuit.

19. The method of claim 11 , wherein the particular sense amplifier provides the sensing current to a plurality of memory cells coupled to a particular bit line during a memory access cycle, and wherein the method comprises:

providing, by the memory controller, the first voltage to the particular sense amplifier to bias the particular bit line to a known voltage level during the pre-charging stage; and

providing, by the memory controller, the second voltage to the particular sense amplifier to limit a variation in the bias of the particular bit line within a known voltage range during the sensing stage.

20. The method of claim 19 , wherein providing the second voltage comprises:

selecting a value of the second voltage to maintain the bias of a particular bit line coupled to the particular sense amplifier at a known voltage level.