IP Library Granted Patent US 10,797,155
Granted Patent B2
US 10,797,155 · App. 15/637,741 · Granted Oct 6, 2020

Semiconductor structure and manufacturing method thereof

Inventor: Zhenhai Zhang (Singapore, SG)
Assignee: UNITED MICROELECTRONICS CORP.
H01L29/6653H01L21/823425H01L21/823468H01L27/088H01L29/401H01L29/665H01L29/6656H01L29/7847H01L29/42324
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Quick Facts
Patent No.
US 10,797,155
App. No.
15/637,741
Granted
Oct 6, 2020
Kind
B2
Abstract

A semiconductor structure and a manufacturing method thereof are provided, wherein the semiconductor structure includes a substrate and gate structures. The gate structures are disposed on the substrate. Each of the gate structures includes a gate, a first spacer and a second spacer. The gate is disposed on the substrate. The first spacer is disposed on a sidewall of the gate. The second spacer is disposed on the first spacer. In a region between two adjacent gate structures, the first spacers are separated from each other, the second spacers are separated from each other, and an upper portion of each of the second spacers has a recess. The semiconductor structure can be used to form a good metal silicide.

Claims (9)

1. A semiconductor structure, comprising:

a substrate;

gate structures, disposed on the substrate, wherein each of the gate structures comprises:

a gate, disposed on the substrate;

a first spacer, disposed on a sidewall of the gate; and

a second spacer, disposed on the first spacer,

wherein the first spacers of two adjacent gate structures of the gate structures are separated from each other, the second spacers of the two adjacent gate structures of the gate structures are separated from each other, an upper portion of each of the second spacers has a recess, an entire surface of the recess is a concave curved surface, the concave curved surface has a first end and a second end higher than the first end, the first end of the concave curved surface is lower than a top of the second spacer, a distance between the concave curved surface and a bottom surface of the second spacer gradually decreases from the second end to the first end and a distance between the bottom surface of the second spacer and the first end is greater than half a distance between the bottom surface of the second spacer and a top of the second spacer; and a metal silicide layer, disposed on the substrate, wherein the two adjacent gate structures are connected by the metal silicide layer.

2. The semiconductor structure according to claim 1 , wherein the first spacer extends between the second spacer and the substrate.

3. The semiconductor structure according to claim 1 , wherein each of the gate structures further comprises a first dielectric layer, and the first dielectric layer is disposed between the gate and the substrate.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 29, 2017
From: ZHANG, ZHENHAI
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 042868/0196 →
Priority Claims (1)
CN 2017 1 0403145 · Jun 1, 2017 · national
Continuity (1)
Related Publication 20180350929A1 · Dec 6, 2018