Phase change memory
View Patent ↗An embodiment of the invention may include a method of forming, and the resulting semiconductor structure. The method may include removing a portion of an M x+1 layer insulator above an M x conductive layer located in an M x layer insulator. The method may include depositing an Mx+1 conductive layer in the removed portion of the M x+1 layer insulator. The method may include removing a portion of Mx+1 conductive layer to form a first portion of M x+1 conductive layer. The method may include forming spacers above the first portion of M x+1 conductive layer and in the removed portion of the M x+1 layer insulator. The method may include forming a second M x+1 conductive layer. The method may include forming a phase change material on the second M x+1 conductive layer.
1. A semiconductor structure comprising:
an M x conductive layer located in an M x layer insulator;
a phase change material heating element located in the M x+1 layer, wherein a width of a top surface of the phase change material heating element is smaller than a width of a bottom surface of the phase change material heating element; and
a phase change material located in a M x+2 layer in contact with the top surface of the phase change material heating element and in the M x+1 layer, wherein the phase change heating element comprises a top portion of an Mx+i layer that is narrower than a bottom portion of the Mx+I layer, and wherein spacers surround the top portion of the Mx+i layer.
2. The semiconductor structure of claim 1 , wherein the top portion of the M x+1 layer and the bottom portion of the M x+1 layer are a uniform structure.
3. The semiconductor structure of claim 2 , wherein there is a void in the bottom portion.
4. The semiconductor structure of claim 1 , wherein the top portion of the M x+1 layer and the bottom portion of the M x+1 layer are independently formed structures.
5. The semiconductor structure of claim 4 , wherein the top portion of the M x+1 layer and the bottom portion of the M x+1 layer are made of different materials.
6. The semiconductor structure of claim 4 , wherein the top portion of the M x+1 layer and the bottom portion of the M x+1 layer are made of the same material.
7. The semiconductor structure of claim 1 , wherein the width of the top portion of the M x+1 layer is approximately 3 nm to approximately 20 nm.
8. The semiconductor structure of claim 7 , wherein the width of the bottom portion of the M x+1 layer is approximately 10 nm to approximately 50 nm.