Architecture for enabling zero value shifting
A system includes an analog memory architecture for performing differential reading. The analog memory architecture includes a weight array including first cross-point devices located at intersections of a first set of conductive column wires and a first set of conductive row wires, and a reference array operatively coupled to the weight array and including second cross-point devices located at intersections of a second set of conductive column wires and a second set of conductive row wires. The second cross-point devices include differential unipolar switching memory devices configured to enable zero-value shifting of the outputs of the first cross-point devices.
1. A system comprising:
an analog memory architecture for performing differential reading, including:
a weight array including first cross-point devices located at intersections of a first set of conductive column wires and a first set of conductive row wires; and
a reference array operatively coupled to the weight array and including second cross-point devices located at intersections of a second set of conductive column wires and a second set of conductive row wires;
the second cross-point devices including differential unipolar switching memory devices configured to enable zero-value shifting of the outputs of the first cross-point devices.
2. The system of claim 1 , wherein the first cross-point devices converge at respective symmetry points.
3. The system of claim 1 , wherein conductance values for each of the first cross-point devices are copied to the reference array.
4. The system of claim 1 , wherein the first and second cross-point devices include resistive processing units (RPUs).
5. The system of claim 1 , further comprising:
a first voltage pulse generator connected to the set of conductive row wires in the weight array; and
a second voltage pulse generator connected to the set of conductive column wires in the weight array.
6. The system of claim 1 , further comprising an analog-to-digital converter (ADC) connected, via an integrator, to the set of conductive column wires in the weight array.
7. The system of claim 1 , wherein the analog memory architecture includes a resistive random-access memory (ReRAM) memory architecture.
8. The system of claim 1 , wherein the analog memory architecture includes a phase-change memory (PCM) memory architecture.
9. A system comprising:
an analog memory architecture for performing differential reading, including:
a weight array including first cross-point devices located at intersections of a first set of conductive column wires and a first set of conductive row wires, wherein the first cross-point devices converge at respective symmetry points;
a first voltage pulse generator connected to the set of conductive row wires in the weight array;
a second voltage pulse generator connected to the set of conductive column wires in the weight array;
an analog-to-digital converter (ADC) connected, via an integrator, to the set of conductive column wires in the weight array; and
a reference array operatively coupled to the weight array and including second cross-point devices located at intersections of a second set of conductive column wires and a second set of conductive row wires;
the second cross-point devices including differential unipolar switching memory devices configured to enable zero-value shifting of the outputs of the first cross-point devices.
10. The system of claim 9 , wherein conductance values for each cross-point device from the weight array are copied to the reference array.
11. The system of claim 9 , wherein the cross-point devices include resistive processing units (RPUs).
12. The system of claim 9 , wherein the analog memory architecture includes a resistive random-access memory (ReRAM) memory architecture.
13. The system of claim 9 , wherein the analog memory architecture includes a phase-change memory (PCM) memory architecture.
14. A method comprising:
applying voltage pulses to first cross-point devices of a weight array of an analog memory architecture for performing differential reading to achieve symmetry point convergence, the first cross-point devices being located at intersections of a first set of conductive column wires and a first set of conductive row wires;
copying conductance values for each of the first cross-point devices to a reference array of the analog memory architecture operatively coupled to the weight array, the reference array including second cross-point devices located at intersections of a second set of conductive column wires and a second set of conductive row wires, wherein the second cross-point devices include differential unipolar switching memory devices; and
enabling zero-value shifting of the outputs of the first cross-point devices using the second cross-point devices.
15. The method of claim 14 , wherein applying the voltage pulses includes applying up and down voltage pulses.
16. The method of claim 14 , wherein the voltage pulses are applied randomly.
17. The method of claim 14 , wherein the voltage pulses are applied in an alternating manner.
18. The method of claim 14 , wherein the conductance values copied to the reference array include zero-weight values.
19. The method of claim 14 , wherein enabling zero-value shifting of the outputs of the first cross-point devices using the second cross-point devices further includes:
applying a signal to both the weight array and the reference array to obtain the outputs of the weight array and outputs of the reference array; and
subtracting the outputs of the weight array from the outputs of the reference array.
20. The method of claim 14 , wherein the cross-point devices include resistive processing units (RPUs).
21. The method of claim 14 , wherein the analog memory architecture includes a resistive random-access memory (ReRAM) memory architecture.
22. The method of claim 14 , wherein the analog memory architecture includes a phase-change memory (PCM) memory architecture.