Memory device
A memory device includes a memory cell array including a plurality of memory cells and a memory controller to control the plurality of memory cells. The memory cell array has a first fuse region including a plurality of first fuse cells having a same structure as the plurality of memory cells and a second fuse region including a plurality of second fuse cells having a structure different from a structure of the plurality of memory cells. The memory controller has a fuse selection circuit selecting one of the first fuse region and the second fuse region.
1. A memory device, comprising:
a memory cell array including a plurality of memory cells, the memory cell array having a first fuse region and a second fuse region, the first fuse region including a plurality of first fuse cells having a structure the same as a structure of the plurality of memory cells, and the second fuse region including a plurality of second fuse cells having a structure different from a structure of the plurality of memory cells; and
a memory controller to control the plurality of memory cells and write fuse data stored in the first fuse region to the second fuse region after an electrical die sort (EDS) test that tests electrical characteristics is completed, the memory controller having a fuse selection circuit to select one of the first fuse region and the second fuse region,
wherein each of the plurality of memory cells and the plurality of first fuse cells includes a data storage element and a switch element connected in series, and
the plurality of memory cells stores data using changes in resistance of the data storage element.
2. The memory device as claimed in claim 1 , wherein the first fuse region is in a center of the memory cell array.
3. The memory device as claimed in claim 1 , wherein the first fuse region and the second fuse region are adjacent to each other in the memory cell array.
4. The memory device as claimed in claim 1 , wherein the first fuse region and the second fuse region are separated from each other in the memory cell array.
5. The memory device as claimed in claim 1 , wherein the plurality of second fuse cells are antifuse cells.
6. The memory device as claimed in claim 1 , wherein the memory controller writes fuse data, stored in the first fuse region, to the second fuse region after the EDS test is completed and before a packaging process is performed.
7. The memory device as claimed in claim 1 , wherein the memory controller writes fuse data for a package test to the first fuse region after the EDS test and a packaging process are completed.
8. The memory device as claimed in claim 7 , wherein the memory controller writes data stored in the first fuse region to the second fuse region after the package test is completed.
9. The memory device as claimed in claim 1 , wherein a number of the plurality of second fuse cells is greater than or equal to a number of the plurality of first fuse cells.
10. A memory device, comprising:
a memory cell array including a plurality of memory cells that store data using changes in resistance, a plurality of electrical fuse cells having a structure the same as a structure of the plurality of memory cells, and a plurality of antifuse cells; and
a fuse selection circuit to select one among the plurality of electrical fuse cells and the plurality of antifuse cells,
wherein the plurality of electrical fuse cells are used as redundancy memory cells for the plurality of memory cells.
11. The memory device as claimed in claim 10 , further comprising:
a page buffer circuit to store data to the memory cell array, and read data stored in the memory cell array,
wherein the page buffer circuit reads data stored in the plurality of electrical fuse cells and writes the data to the plurality of antifuse cells, when a predetermined test procedure is terminated.
12. The memory device as claimed in claim 11 , wherein the fuse selection circuit selects the plurality of electrical fuse cells before the predetermined test procedure is terminated and selects the plurality of antifuse cells when the predetermined test procedure is terminated.
13. The memory device as claimed in claim 11 , wherein the predetermined test procedure includes at least one of an electrical die sort (EDS) test procedure and a package test procedure.
14. A memory device, comprising:
a plurality of memory cells to store data using changes in resistance;
a plurality of first fuse cells having a structure the same as a structure of the plurality of memory cells;
a plurality of second fuse cells having a structure different from a structure of the plurality of memory cells; and
a memory controller to write fuse data stored in the plurality of first fuse cells to the plurality of second fuse cells, and to use the plurality of first fuse cells as redundancy memory cells for the plurality of memory cells.
15. The memory device as claimed in claim 14 , wherein the plurality of first fuse cells are electrical fuse cells, and the plurality of second fuse cells are antifuse cells.